Subject: WW36 System Design Studio - Dev coordination - meeting notes!
From: "Rajan, Vivek K" <[email-masked]>
To: "Abe, Takuya" <[email-masked]>, systemdesignstudio <[email-masked]>, "Krishnamoorthy, Ambika" <[email-masked]>, "Metz Phd, Werner" <[email-masked]>, "Arafa, Mohamed" <[email-masked]>, "Majhi, Prashant" <[email-masked]>
Cc: "Surana, Satish K" <[email-masked]>, "Klowden, Daniel S" <[email-masked]>, "Immaneni, Lalitha" <[email-masked]>, "Venkata, Giri" <[email-masked]>, "Chatterjee, Deb" <[email-masked]>, "Munoz, Robert" <[email-masked]>, "Karnik, Tanay" <[email-masked]>, "Rothstein, Chris" <[email-masked]>, "Kwatra, Atul" <[email-masked]>, "Brennan, Bob" <[email-masked]>, "Huang, Margaret" <[email-masked]>, "Lalwaney, Poornima" <[email-masked]>, "Iyer, Bala" <[email-masked]>, "Rao, Navneet" <na
Date: Tue, 5 Sep 2023 19:15:17 +0000

WW36 2023 System Studio Virtual Team Meeting

Teams Share-point Link: https://teams.microsoft.com/l/team/19%3abK0MGqmIvfKBfMR0B2-vLgbbqj1_0Jd2fdZ5fjSXCXM1%40thread.tacv2/conversations?groupId=090e4e92-779d-4ce2-a052-003585d76094&tenantId=46c98d88-e344-4ed4-8496-4ed7712e255d

1. Opens

*       SNPS F2F this week (WW36.Thursday)

   *    Agenda for SNPS F2F

#

Topic / Focus Area

Presenter(s)

Duration

Discussion Expectations

0

Introductions

All

11:00 - 11:15

Meet and Greet

Introductions

1

System Design Studio [RECAP and discussion]

Vivek and Tanay @ Intel

11:15 - 12:30

Overview and goals for System Design Studio

Next 6 months roadmap: minimum value product

POC plans (thru an actual design)

2

Lunch

ALL

12:30 - 13:45

3

Sub-Topic #1: needs and requirements for Common Model / Intermediate Representation

Sub-Topic #2: HW and SW modeling and co-design

Sub-Topic #3: Solver and multi-physics engines integration

Intel + SNPS

13:45 - 15:00

Options and (potential) directions

Intended usage-models

API based integration

Evolving the usage-model with a POC

4

SNPS Tool Chain and Solution mapping to System Studio

SNPS

15:00 - 16:00

What tools, flows exists today that can enable usage-models for System Studio

What needs enablement, new work, tying existing assets, other approach

5

How we (Intel and SNPS) collaborate together to release System Studio Vision?

Intel + SNPS

16:00 - 17:30pm

Who does what (Intel, SNPS, Industry, Open-Standards, other ideas)

Engagement model with SNPS (value-prop, differentiation, other considerations)

*       Satish and Vivek met with CDNS EDA architect on next steps for SW architecture and engagement

   *    See meeting summary from CDNS Architect (Guru) at the bottom of this thread ... [we discussed the interpretation of the feedback during meeting]
   *    Any feedback and comments
   *    AR: Ask CDNS to come-up with tool/map for example that Intel sent

   2. EDA R&R and next-steps with CDNS and SNPS - discussion with core-team

*       There is ask from each of the EDA, what is their R&R. How do EDA contribute
*       See slides as part of:   SW ARCH System Studio.pptx<https://intel.sharepoint.com/:p:/r/sites/systemsstudiotslrp/Shared%20Documents/General/DEVELOPMENT/SW%20ARCH%20System%20Studio.pptx?d=w57a7d207381d42f4acbab967bec8d52e&csf=1&web=1&e=KIKmlV> (EDA R&R section)

3. SW Architecture Discussion for System Studio (including steady-state EDA R&R and foundry customer usage)

*       See PPT:  SW ARCH System Studio.pptx<https://intel.sharepoint.com/:p:/r/sites/systemsstudiotslrp/Shared%20Documents/General/DEVELOPMENT/SW%20ARCH%20System%20Studio.pptx?d=w57a7d207381d42f4acbab967bec8d52e&csf=1&web=1&e=KIKmlV>
*       Need feedback and further deep-dive on fine-points of SW architecture

=======================================================================================================================================================================================================

From: Guru Rao [email-masked]<mailto:[email-masked]>

Sent: Saturday, September 2, 2023 1:25 PM

To: Rajan, Vivek K [email-masked]<mailto:[email-masked]>; Surana, Satish K [email-masked]<mailto:[email-masked]>; ksubram [email-masked]<mailto:[email-masked]>; Chen, Pinhong [email-masked]<mailto:[email-masked]>; nkaul [email-masked]<mailto:[email-masked]>; Venkat Thanvantri [email-masked]<mailto:[email-masked]>

Subject: Meeting notes - Intel/Cadence

Hi Vivek and Satish

Here are my notes from our discussion yesterday. Thanks for the open and constructive discussion - you answered some of my questions and hopefully also addressed some of Pinhong's concerns.

1.      It was not clear to us what Intel expects from Cadence given that our current suite of tools focusses exclusively on the implementation of chips, packages and systems. Granted that our package and systems implementation story is still a work in progress, we are many years into a multi-year roadmap around established design repositories and a combination of industry standard and proprietary interchange formats. Changing strategies at this point is a very difficult sell.
2.      You clarified that all these discussions are about a completely new tool that is complimentary to/different from the implementation and verification tools that EDA companies like Cadence provide today. When starting a new design, Intel spends several quarters in an exploration phase where hundreds of decisions are made that affect hardware and firmware partitioning, technology choices and interfaces. System Studio is envisioned to be an exploration cockpit for this phase that natively supports collaboration and works with pre-certified repositories of IP and incomplete/evolving design/technology information. The challenges of building such a system are different than the ones we have to deal with in our traditional business. We spend time building scalable and accurate representations for implementation and verification - our customers expect us to support larger designs and more advanced technologies with every release. The emphasis of System Studio is on modeling flexibility and collaboration rather than scale and accuracy.
3.      As part of the thought exercise to understand what goes into a model, you talked about how you are working backwards from a recently completed system that took 4 years to complete. The system has been completely implemented and verified. You are working with different groups and imagining what the models would have looked like at various stages of the 4 year cycle and stripping out the details while preserving the interfaces and behavioral models - this would become a pilot testcase.
4.      You showed a diagram of all the tools involved in this exploration phase today. These are a combination of internally/externally developed tools/scripts that take different inputs and generate outputs/reports in various formats. Each set of tools is used by a set of specialists in areas like Cost, KPI, Thermal, Power, SI and the lack of interoperability between these areas serializes the steps and impacts their ability to collaborate. System Studio proposes a general Visual Code like framework where tools work off and update a common IR (Intermediate Representation). This should allow domain specialists to collaborate and do faster what-if analysis for various system scenarios and is expected to improve efficiency and turn around during the exploration phase.
5.      You also shared a case study that showed specific system tradeoff questions you were trying to answer during this exploration phase. In one scenario, you were trying to understand the impact of firmware turning off different cores based on workload - the benefits/costs on power and thermal can only be answered if there is support for combining software and hardware models along with co-simulation and power/thermal analysis. We need to dive into this scenario a lot more to understand what tools and interfaces are required.
6.      We can continue this discussion at the architecture level and flush out more details - but the question that we will need to answer for concrete support within Cadence is how we are expected to help. Do you need us to put this entire solution together? Or do you want us to work with a company like JETX to implement such a tool? Or would you like us to provide support while you and JETX work together? The answer will determine how much support and resources we need within Cadence to help Intel.

Guruprasad Rao

Product Architecture Team, SPB

Cadence Design Systems

San Jose, CA

(408)-570-3897

-----Original Appointment-----
From: Rajan, Vivek K
Sent: Tuesday, July 11, 2023 10:17 PM
To: Abe, Takuya; Rajan, Vivek K; systemdesignstudio; Krishnamoorthy, Ambika; Metz Phd, Werner; Arafa, Mohamed; Majhi, Prashant
Cc: Surana, Satish K; Klowden, Daniel S; Immaneni, Lalitha; Venkata, Giri; Chatterjee, Deb; Munoz, Robert; Karnik, Tanay; Rothstein, Chris; Kwatra, Atul; Brennan, Bob; Huang, Margaret; Lalwaney, Poornima; Iyer, Bala; Rao, Navneet; Kalavai, Nanda G Kumar; Prashanth, Sakthi; Tsunami, Daniel; Viswanath, Ram S; Vartak, Adish; Neal, Nick; Peng, Chung-Ching; Aboud, Fadi
Subject: WW36 System Design Studio - Dev coordination - agenda below
When: Tuesday, September 5, 2023 11:05 AM-12:00 PM (UTC-08:00) Pacific Time (US & Canada).
Where: Microsoft Teams Meeting

Teams Share-point Link: https://teams.microsoft.com/l/team/19%3abK0MGqmIvfKBfMR0B2-vLgbbqj1_0Jd2fdZ5fjSXCXM1%40thread.tacv2/conversations?groupId=090e4e92-779d-4ce2-a052-003585d76094&tenantId=46c98d88-e344-4ed4-8496-4ed7712e255d

1. Opens

2. EDA R&R and next-steps with CDNS and SNPS - discussion with core-team

3. SW Architecture Discussion for System Studio (including steady-state EDA R&R and foundry customer usage)

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