Intel Confidential Copyright 2021 Intel Corporation. The information contained herein is the proprietary and confidential information of Intel or its licensors, and is supplied subject to, and may be used only in accordance with, previously executed agreements with Intel. EXCEPT AS MAY OTHERWISE BE AGREED IN WRITING: (1) ALL MATERIALS FURNISHED BY INTEL HEREUNDER ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND; (2) INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY; AND (3) INTEL WILL NOT BE LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS, INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY, CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE. Datasheet Template Revision 2.1.5 IP Tag Information & Cell_ID ip7631hdusplr8192x160m4b8s0r0p0d0 & Cell_Type MemoryIP & Date_Time Wed Jun 30 2021 09:40:45 & Product c76hdusplr & Tag_Spec 1.0 & Technology P1276.31 & Vendor Intel Corporation & Version r1.1.0 & _Memory_Name_Generated ip7631hdusplr8192x160m4b8s0r0p0d0 Order Information BK = 8 CM = 4 NB = 160 NW = 8192 PME = 0 WBE = 0 memoryName = ip7631hdusplr8192x160m4b8s0r0p0d0 redCol = 0 redRow = 0 Configuration Data Parameter | Value | Unit | Description ================================================================================================================================ Technology | P1276.31 | | -------------------------------------------------------------------------------------------------------------------------------- Memory Type | HDUSPLR | | -------------------------------------------------------------------------------------------------------------------------------- Compiler Name | c76hdusplr | | -------------------------------------------------------------------------------------------------------------------------------- Compiler Version | r1.1.0 | | -------------------------------------------------------------------------------------------------------------------------------- Ports | One Read/Write Port | | -------------------------------------------------------------------------------------------------------------------------------- Interface | Rising Edge Synchronous | | -------------------------------------------------------------------------------------------------------------------------------- Instance Name | ip7631hdusplr8192x160m4b8s0r0p0d0 | | -------------------------------------------------------------------------------------------------------------------------------- Instance Name Generated | ip7631hdusplr8192x160m4b8s0r0p0d0 | | -------------------------------------------------------------------------------------------------------------------------------- Total Bit Count Incl Repair | 1310720 | bits | Total bit count including repair bits -------------------------------------------------------------------------------------------------------------------------------- Word Depth | 8192 | | Number of logical words (NW) -------------------------------------------------------------------------------------------------------------------------------- Word Width | 160 | | Number of logical bits per word (NB) -------------------------------------------------------------------------------------------------------------------------------- Physical Word Depth | 8192 | | Number of physical words including repair -------------------------------------------------------------------------------------------------------------------------------- Physical Word Width | 160 | | Number of physical bits per word including repair -------------------------------------------------------------------------------------------------------------------------------- Column Mux | 4 | | Column Mux Size (CM) -------------------------------------------------------------------------------------------------------------------------------- Banks | 8 | | Number of Banks (BK) -------------------------------------------------------------------------------------------------------------------------------- Center Decode | Yes | | Center Decoder Enable -------------------------------------------------------------------------------------------------------------------------------- Bit Enabled Write | No | | Not Available (WBE) -------------------------------------------------------------------------------------------------------------------------------- Column Redundancy | No | | Column Redundancy Enable (redCol) -------------------------------------------------------------------------------------------------------------------------------- Row Redundancy | No | | Row Redundancy Enable (redRow) -------------------------------------------------------------------------------------------------------------------------------- BIST Enable | No | | BIST Enable -------------------------------------------------------------------------------------------------------------------------------- Scan Enable | No | | Scan Enable -------------------------------------------------------------------------------------------------------------------------------- Dual Supply | No | | Dual Rail Enable -------------------------------------------------------------------------------------------------------------------------------- Write Assist | Yes | | Write Assist Feature Included -------------------------------------------------------------------------------------------------------------------------------- Deep Sleep | No | | Deep Sleep Enable (PME) -------------------------------------------------------------------------------------------------------------------------------- Array Sleep | No | | Array Sleep Enable -------------------------------------------------------------------------------------------------------------------------------- Periphery Shutoff | No | | Periphery Shut Off Enable (PME) -------------------------------------------------------------------------------------------------------------------------------- Shut Off | No | | Shut-off Enable (PME) -------------------------------------------------------------------------------------------------------------------------------- Periphery Vt | Mix | | Periphery voltage option -------------------------------------------------------------------------------------------------------------------------------- Timing De-rate Applied | Yes | | Timing De-rate Enable -------------------------------------------------------------------------------------------------------------------------------- Area Data Parameter | Value | Unit | Description ================================================================================================================================ Bitcell Area | 0.030000 | um^2 | Area per BitCell -------------------------------------------------------------------------------------------------------------------------------- Memory Area (WidthxHeight) | 48944.412 (243.650x200.880) | um^2 | Area not including halo -------------------------------------------------------------------------------------------------------------------------------- Total Macro Area (WidthxHeight) | 49172.112 (244.200x201.360) | um^2 | Area including halo -------------------------------------------------------------------------------------------------------------------------------- Pin Interface Pin Name | Description | Direction | Power Domain | Registered ============================================================================================================================================================================== Functional Mode Pins ============================================================================================================================================================================== clk | External clock in functional mode | IN | vddp | NO ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ stbyp | Test pin to bypass self-time circuit. External clock control the read read/write operation | IN | vddp | NO ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ adr[12:0] | Address Input during functional mode | IN | vddp | Yes ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ din[159:0] | Data Input bus in functional mode | IN | vddp | Yes ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ren | Read Enable pin | IN | vddp | Yes ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ wen | Write Enable input | IN | vddp | Yes ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ async_reset | Output reset signal. '0' normal operation, '1' resets memory output to 0. | IN | vddp | NO ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ q[159:0] | Data output bus. When enabled, it generates the contents of the memory location addressed by the Address Input signals | OUT | vddp | Yes ============================================================================================================================================================================== Margin and Assist Control Pins ============================================================================================================================================================================== wa[2:0] | Write assist bias fuse signal settings | IN | vddp | NO ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ra[1:0] | Read assist fuse setting | IN | vddp | NO ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ wpulse[2:0] | Write assist pulse fuse setting | IN | vddp | NO ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ mce | Margin Control Enable | IN | vddp | NO ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ rmce[3:0] | Read margin input for read margin settings | IN | vddp | NO ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ wmce[1:0] | Write margin input for write margin settings | IN | vddp | NO ============================================================================================================================================================================== Power Management Mode Pins ============================================================================================================================================================================== arysleep | Must be '0' to disable sleep at current pvt. | IN | vddp | NO ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ sbc[1:0] | Sleep bias settings and override | IN | vddp | NO ============================================================================================================================================================================== Power Pins ============================================================================================================================================================================== vddp | Memory array and periphery supply | IN | | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ vss | Common ground pin | INOUT | | ============================================================================================================================================================================== Timing Characterization Data Parameter | Description | Units | Notes | tttt_0.85v_0.85v_100c =========================================================================================================== Process Corner | | | | tttt ----------------------------------------------------------------------------------------------------------- Periphery Voltage | vddp | Volt | | 0.85 ----------------------------------------------------------------------------------------------------------- Array Voltage | vddp | Volt | | 0.85 ----------------------------------------------------------------------------------------------------------- Temperature | | Deg C | | 100 ----------------------------------------------------------------------------------------------------------- Output Capacitance | Characterized Output Capacitance | fF | | 5.000 ----------------------------------------------------------------------------------------------------------- Input Slew | Characterized Data Input Slope | ps | | 5.000 ----------------------------------------------------------------------------------------------------------- Clock Slew | Characterized Clock Slope | ps | | 5.000 =========================================================================================================== Timing Characterization: Fastest Valid Timing Mode =========================================================================================================== Tcc_default | Cycle Time (Default MCE=0) | ps | | 721.086 ----------------------------------------------------------------------------------------------------------- Tcc_optimal | Cycle Time (Optimal Timing Mode Setting) | ps | | 692.541 ----------------------------------------------------------------------------------------------------------- TM_optimal | Optimal Timing Mode Setting for PVT | | | TM3 ----------------------------------------------------------------------------------------------------------- Tcc_1sigma | 1 sigma variation Tcc offset | ps | | 6.233 ----------------------------------------------------------------------------------------------------------- Tch | Min clk high pulse width | ps | | 89.000 ----------------------------------------------------------------------------------------------------------- Tcl | Min clk low pulse width | ps | | 77.000 ----------------------------------------------------------------------------------------------------------- Tcq_default | clk to q Delay (Default MCE=0) | ps | | 494.572 ----------------------------------------------------------------------------------------------------------- Tcq_optimal | clk to q Delay (Optimal Timing Mode Setting) | ps | | 494.851 ----------------------------------------------------------------------------------------------------------- Tcqx | q data out hold time after clk rises | ps | | 340.069 ----------------------------------------------------------------------------------------------------------- Tac | Address Setup | ps | | 181.772 ----------------------------------------------------------------------------------------------------------- Tcax | Address Hold | ps | | 71.033 ----------------------------------------------------------------------------------------------------------- Tdc | Data Setup | ps | | 13.901 ----------------------------------------------------------------------------------------------------------- Tcdx | Data Hold | ps | | 166.610 ----------------------------------------------------------------------------------------------------------- Twc | Write Enable Setup | ps | | 153.917 ----------------------------------------------------------------------------------------------------------- Tcwx | Write Enable Hold | ps | | 61.617 ----------------------------------------------------------------------------------------------------------- Trc | Read Enable Setup | ps | | 108.519 ----------------------------------------------------------------------------------------------------------- Tcrx | Read Enable Hold | ps | | 65.123 ----------------------------------------------------------------------------------------------------------- Twbc | Bit Enable Write Setup | ps | | * ----------------------------------------------------------------------------------------------------------- Tcwbx | Bit Enable Write Hold | ps | | * ----------------------------------------------------------------------------------------------------------- Tsdoutr | shutoff rising to shutoffout rising delay | ps | | * ----------------------------------------------------------------------------------------------------------- Tsdoutf | shutoff falling to shutoffout falling delay | ps | | * ----------------------------------------------------------------------------------------------------------- Tlsi | Time to fully enter arysleep mode | ps | | * ----------------------------------------------------------------------------------------------------------- Tdsi | Time to fully enter pshutoff mode | ps | | * ----------------------------------------------------------------------------------------------------------- Tsdi | Time to fully enter shutoff mode | ps | | * ----------------------------------------------------------------------------------------------------------- Tlsexit | Time to exit arysleep mode | ps | | * ----------------------------------------------------------------------------------------------------------- Tpsexit | Time to exit pshutoff mode | ps | | * ----------------------------------------------------------------------------------------------------------- Tsdexit | Time to exit shutoff mode | ps | | * =========================================================================================================== Timing Characterization: All Timing Modes =========================================================================================================== Tcc_tm1 | Cycle Time when tm1 | ps | | 721.086 ----------------------------------------------------------------------------------------------------------- Tcc_tm2 | Cycle Time when tm2 | ps | | 730.433 ----------------------------------------------------------------------------------------------------------- Tcc_tm3 | Cycle Time when tm3 | ps | | 692.541 ----------------------------------------------------------------------------------------------------------- Tcq_tm1 | Read access time when tm1 | ps | | 494.572 ----------------------------------------------------------------------------------------------------------- Tcq_tm2 | Read access time when tm2 | ps | | 504.196 ----------------------------------------------------------------------------------------------------------- Tcq_tm3 | Read access time when tm3 | ps | | 494.851 =========================================================================================================== Leakage Characterization Data Parameter | Description | Units | Notes | tttt_0.85v_0.85v_100c ====================================================================================================================================================================== Process Corner | | | | tttt ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- Periphery Voltage | vddp | Volt | | 0.85 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- Array Voltage | vddp | Volt | | 0.85 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- Temperature | | Deg C | | 100 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- Output Capacitance | Characterized Output Capacitance | fF | | 5.000 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- Input Slew | Characterized Data Input Slope | ps | | 5.000 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- Clock Slew | Characterized Clock Slope | ps | | 5.000 ====================================================================================================================================================================== Characterization Bitcell Leakage Power ====================================================================================================================================================================== PLeak_bit | Leakage Power for a single bit | uW | 1 | 0.0009641 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_bits | Leakage Power for all bits | uW | 1 | 1263.705 ====================================================================================================================================================================== Characterization Total Leakage Power ====================================================================================================================================================================== PLeak_all | Total leakage power for all supplies arysleep=0, pshutoff=0, shutoff=0, sbc[1:0]=XX | uW | 1 | 1935.733 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_ls_00_all | Total Sleep leakage power for all supplies arysleep=1, pshutoff=0, shutoff=0, sbc[1:0]=00 | uW | 1 | * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_ls_01_all | Total Sleep leakage power for all supplies arysleep=1, pshutoff=0, shutoff=0, sbc[1:0]=01 | uW | 1 | * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_ls_10_all | Total Sleep leakage power for all supplies arysleep=1, pshutoff=0, shutoff=0, sbc[1:0]=10 | uW | 1 | * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_ls_11_all | Total Sleep leakage power for all supplies arysleep=1, pshutoff=0, shutoff=0, sbc[1:0]=11 | uW | 1 | * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_ps_all | Total Periphery Shut Down leakage power for all supplies arysleep=0, pshutoff=1, shutoff=0, sbc[1:0]=XX | uW | 1 | * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_ds_00_all | Total Deep Sleep leakage power for all supplies arysleep=1, pshutoff=1, shutoff=0, sbc[1:0]=00 | uW | 1 | * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_ds_01_all | Total Deep Sleep leakage power for all supplies arysleep=1, pshutoff=1, shutoff=0, sbc[1:0]=01 | uW | 1 | * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_ds_10_all | Total Deep Sleep leakage power for all supplies arysleep=1, pshutoff=1, shutoff=0, sbc[1:0]=10 | uW | 1 | * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_ds_11_all | Total Deep Sleep leakage power for all supplies arysleep=1, pshutoff=1, shutoff=0, sbc[1:0]=11 | uW | 1 | * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- PLeak_sd_all | Total Shut Down leakage power for all supplies arysleep=X, pshutoff=X, shutoff=1, sbc[1:0]=XX | uW | 1 | * ====================================================================================================================================================================== Dynamic Power Characterization Data Parameter | Description | Units | Notes | tttt_0.85v_0.85v_100c ================================================================================================================ Process Corner | | | | tttt ---------------------------------------------------------------------------------------------------------------- Periphery Voltage | vddp | Volt | | 0.85 ---------------------------------------------------------------------------------------------------------------- Array Voltage | vddp | Volt | | 0.85 ---------------------------------------------------------------------------------------------------------------- Temperature | | Deg C | | 100 ---------------------------------------------------------------------------------------------------------------- Output Capacitance | Characterized Output Capacitance | fF | | 5.000 ---------------------------------------------------------------------------------------------------------------- Input Slew | Characterized Data Input Slope | ps | | 5.000 ---------------------------------------------------------------------------------------------------------------- Clock Slew | Characterized Clock Slope | ps | | 5.000 ================================================================================================================ Characterization Total Dynamic Energy for Optimal Assist and Timing Mode setting for Each PVT ================================================================================================================ Pread_typ | Typical Read Operation Energy | uW/GHz | 2,5,6 | 10580.623 ---------------------------------------------------------------------------------------------------------------- Pread_wc | Worst Case Read Operation Energy | uW/GHz | 2,8,9 | 22914.935 ---------------------------------------------------------------------------------------------------------------- Pwrite_typ | Typical Write Operation Energy | uW/GHz | 2,5,7 | 17902.809 ---------------------------------------------------------------------------------------------------------------- Pwrite_wc | Worst Case Write Operation Energy | uW/GHz | 2,8,10 | 41464.966 ---------------------------------------------------------------------------------------------------------------- Padr_write_all | adr Bus Energy on all supplies when wen is high | uW/GHz | 2,3 | 2738.171 ---------------------------------------------------------------------------------------------------------------- Padr_read_all | adr Bus Energy on all supplies when ren is high | uW/GHz | 2,3 | 2738.171 ---------------------------------------------------------------------------------------------------------------- Pclk_write_all | clk Energy on all supplies when wen is high | uW/GHz | 2,4 | 23072.185 ---------------------------------------------------------------------------------------------------------------- Pclk_read_all | clk Energy on all supplies when ren is high | uW/GHz | 2,4 | 19381.636 ---------------------------------------------------------------------------------------------------------------- Pren_all | ren Energy on all supplies | uW/GHz | 2,3 | 25.921 ---------------------------------------------------------------------------------------------------------------- Pwen_all | wen Energy on all supplies | uW/GHz | 2,3 | 7074.086 ---------------------------------------------------------------------------------------------------------------- Pdin_all | din Bus Energy on all supplies | uW/GHz | 2,3 | 8580.523 ---------------------------------------------------------------------------------------------------------------- Pq_all | q Bus Energy on all supplies | uW/GHz | 2,3 | 769.207 ---------------------------------------------------------------------------------------------------------------- Parysleep_all | arysleep pin toggle energy | uW/GHz | 2,3 | * ---------------------------------------------------------------------------------------------------------------- Ppshutoff_all | pshutoff pin toggle energy | uW/GHz | 2,3 | * ---------------------------------------------------------------------------------------------------------------- Pshutoff_all | shutoff pin toggle energy | uW/GHz | 2,3 | * ================================================================================================================ Max Current Characterization Data Parameter | Description | Units | Notes | tttt_0.85v_0.85v_100c ====================================================================================================================== Process Corner | | | | tttt ---------------------------------------------------------------------------------------------------------------------- Periphery Voltage | vddp | Volt | | 0.85 ---------------------------------------------------------------------------------------------------------------------- Array Voltage | vddp | Volt | | 0.85 ---------------------------------------------------------------------------------------------------------------------- Temperature | | Deg C | | 100 ---------------------------------------------------------------------------------------------------------------------- Output Capacitance | Characterized Output Capacitance | fF | | 5.000 ---------------------------------------------------------------------------------------------------------------------- Input Slew | Characterized Data Input Slope | ps | | 5.000 ---------------------------------------------------------------------------------------------------------------------- Clock Slew | Characterized Clock Slope | ps | | 5.000 ====================================================================================================================== Characterization vddp Max Current ====================================================================================================================== Imax_read_vddp | Maximum current during read operation on vddp | mA | | 168.048 ---------------------------------------------------------------------------------------------------------------------- Imax_write_vddp | Maximum current during write operation on vddp | mA | | 188.995 ---------------------------------------------------------------------------------------------------------------------- Imax_pshutoff_exit_vddp | Maximum current when exiting pshutoff mode on vddp | mA | | * ---------------------------------------------------------------------------------------------------------------------- Imax_shutoff_exit_vddp | Maximum current when exiting shutoff mode on vddp | mA | | * ====================================================================================================================== Pin Capacitance Parameter | Description | Units | Notes | tttt_0.85v_0.85v_100c ======================================================================================================= Process Corner | | | | tttt ------------------------------------------------------------------------------------------------------- Periphery Voltage | vddp | Volt | | 0.85 ------------------------------------------------------------------------------------------------------- Array Voltage | vddp | Volt | | 0.85 ------------------------------------------------------------------------------------------------------- Temperature | | Deg C | | 100 ------------------------------------------------------------------------------------------------------- Output Capacitance | Characterized Output Capacitance | fF | | 5.000 ------------------------------------------------------------------------------------------------------- Input Slew | Characterized Data Input Slope | ps | | 5.000 ------------------------------------------------------------------------------------------------------- Clock Slew | Characterized Clock Slope | ps | | 5.000 ======================================================================================================= Pin Capacitance Parameters (for individual pins, busses are not combined into a single value ======================================================================================================= Cclk | clk Pin Capacitance | fF | | 2.825 ------------------------------------------------------------------------------------------------------- Cdin | Data Pin Capacitance (individual pin) | fF | | 1.646 ------------------------------------------------------------------------------------------------------- Cadr | Address Pin Capacitance (individual pin) | fF | | 1.211 ------------------------------------------------------------------------------------------------------- Cwen | wen Pin Capacitance | fF | | 0.859 ------------------------------------------------------------------------------------------------------- Cren | ren Pin Capacitance | fF | | 1.050 ======================================================================================================= Notes: 1. Static power includes Sub-threshold and junction leakage 2. Dynamic energy does not include Sub-threshold and junction leakage and external load 3. Dynamic energy is reported as the average of falling and rising values for non-clock pins 4. Dynamic energy is reported as the sum of falling and rising values for clock pins 5. Dynamic Typical Pread/Pwrite Operation Energy Assumptions: - Alternate cycles are active - 1/2 Address bits switching - 1/2 Data bits switching - Applicable read or write enable bit switching - Average of read 1/read 0 - Average of address high/low 6. Typical Read Energy Equation: Pread_typ = 0.5*(Pclkrd+0.5*Pdout+0.5*Pradr+Pren) 7. Typical Write Energy Equation: Pwrite_typ = 0.5*(Pclkwr+0.5*Pdin+0.5*Pwadr+Pwen) 8. Dynamic Worst Case Pread/Pwrite Operation Energy Assumptions: - All cycles are active - All Address bits switching - All Data bits switching - Average of read 1/read 0 - Average of address high/low 9. Worst Case Read Energy Equation: Pread_wc = Pclkrd+Pdout+Pradr+Pren 10. Worst Case Write Energy Equation: Pwrite_wc = Pclkwr+Pdin+Pwadr+Pwen Toggle energy is expressed in uW/GHz which is equivalent to fJ or nW/MHz 1 Joule = 1 Watt * 1 Second 1 fJ = 1 uW * 1 ns = 1 uW/GHz 1 fJ = 1 nW * 1 us = 1 nW/MHz