Beyond 10s
architecture pathfinding

Wk32/2017 Key message:

#1 Silicon status has been reviewed.
Next lot out is PM-Al doped for void recovery. Other running trials are
In-SDrev12, WC PM top lamina and SiN doped SD.

#2 Lot 9897782.003 with IOSOD/Es has
been presented. IO-SOD put on hold due to the inability to recover fill related
set degradation with the electrode package. Filling work is going ahead with
vendors to provide new chemicals other than IO-SOD. Forecast to launch the first
SWR is 4 weeks (iWW36) and it will be a S15 swap lot. After discussion, no need
to try IO-SOD on rev 7.64.

#3 Te skew lot 9897752.003 WLR summary has been
presented. Te poor trials clearly showed
penalty on window also at WLR. Main messages are: Annealing @67 effect consistent with expectations: Tgrowth,
set-ability and E3 shift improve with the annealing @67 (Te POR and -6%); TD
decreases its capability, lower window. N2
flow variation: Almost no impact of this trial on WLR. Te trends (-9% Te data na): Windows trending with Te, following
expectations; Set-ability: Set knee sigma get worse for -6% trials correlating
with opens; Intrinsic set-ability slightly improves for low Te trials (check
Ge/Sb content); Thermal disturb -6% Te improves TD but no clear explanation
from set-ability, over-stress and in-line CD (check with PI).

#4 TCAD capacitance scaling simulation
has been presented for MTSrev0. Main messages are: 1) lateral capacitance does
scale with 1X, thus showing that the fringing contribution is negligible 2)
cell capacitance (WL2BL) scales with area factor (0.5X) 3) PM status (amorphous
or crystal) has an impact on the value of the capacitance of the inner
connections. Recommendations: 1) to check effect of PM status on measurements
(mongomono and coombs) 2) to report in DTS a mixed patter related capacitance
for inner connections.

#5 Tset intrinsic scaling calculation
has been presented. From nucleation theory, intrinsic tseed is expected to
increase for 30s to 2X. This probably will require a material adjustment/optimization.

Wk31/2017 Key message:

#1 Te skew lot 9897752.003 probe summary has been
shown (trial only at deck0). Key messages are:
1) 9% Te: not evaluable for open issues 2) Trail with -6% Te:  central part of the wafers strongly affected
by open issue; decreases deltaVT (-110mV due to reset VT lowering) and set knee
(-0.3sigma, 780ns); Set-ability is slightly higher than POR, comparable with
-3% Te trial; thermal disturb capability improves.  Trial with -3% Te: slightly faster
set-ability, -50mV on deltaVT, thermal disturb improved. Annealing @67: faster
set-ability both with POR Te and -6% Te. Increasing the N2 flow, the effect of
-6% Te are confirmed. Set-ability tail on -6% Te trial are reduced with N2 flow
enhancement. Follow-up PFA to understand strange behavior of group -6% Te in
the window versus set-ability line should be addressed. Recommendation to wait
for WLR especially for WD assessment and the next skew lot that will have the
trial on the upper deck.

#2 Follow-up SWR on AlO SD cosputter has been
presented. SWR will contain a direct comparison on SDv12 monolitic versus SDv12
by co-sputter (SDv12-3C). The AlO cosputter trial is built on SDv12-3C with
doping down to 0.7%. AlO 0.7% is also tried crossed with 2% In in SDv12-3C.

#3 In-SD window study has been
performed. Original aim was to check the window benefit with In doping in
virgin arrays to minimize the leakage effect. Unfortunately, the probe flow
does lot leave untouched dice, preventing this analysis. An attempt to recover
the high Vt (low leakage) state was performed with 2h @250C bake. The analysis
confirmed a larger window for 2% In SD, but some concerns have been raised
about this methodology. Recommendation to repeat the experiment of one on the
next lots where we should ask the probe team to leave some virgin dice.

#4 Summary of process toggles on
Ihold has been shown. The analysis was performed both on specific trials lots
(seal/Es/PM) and on the trend-chart variations of the last year tested
material. Main conclusion is: CN in the electrodes (BE/ME/TE) and increased
PM/SD thicknesses are able to toggle the Ihold in the right direction
(decreasing it). The effects can be added and the entity of each change is in
the order of few uA.

#5 Rev 7.64 extended bipolar ON-IV
has been shown. Up/down curves are anomalous and the origin of the issue must
be clarified and measurements repeated. Qualitatively, the measurements confirm
the 2.7V initial Von and the lower Von in reverse bias.

Wk29/2017 Key message:

#1 Priorities for next quarter have
been reviewed. Activities will be developed in three main areas: 1) set-up of
s26 off-pitch CD shrink, possibly down to 14 nm. This will allow to validate
key cell performances for DTS and s37 first design review, targeting October
2017. 2) work on DTS with DT, validating MTSrev0/DTSrev0 consistency through
simulation projections and dedicated characterizations. 3) elaborate on a
MTSrev1 focus on a cell design more feasible from integration perspective.

#2 Follow-up on WC activities have
been discussed. A L3 lot has been defined with a SWR with top WC lamina with W
content down to 20%. Highlighted a risk of high interface resistance on low W
content trials. Lot to be run on 7.64.

#3 WLR of AlO lamina lot 9897742.003
has been shared. WLR confirmed the probe toggles but with the window gain of
AlO trials that is lost through cycling. The only trial that seems to toggle
most of the cell metrics in the positive directions is the 1% AlO. Request to
have a table with a direct comparison between 6E and 4E groups to decide if we
want an additional lot based on SDrev12 to re-check the benefit on the actual
SD version. Analysis has been done and the file shared off-line. Based on the
good window toggle, recommendation is to repeat the 1% AlO trial on SDrev12. In
discussion if this can be done with the actual chamber set-up.

#4 PM Vt versus set-ability trends
has been reviewed. From scaling perspective, a significant worsening of
set-ability and +150 mV gain @RT in window are expected. So, with actual
scaling approach, the cell performance working point will land on a different
position in the set-ability versus window trade-off. To re-balance it at the
s26 working point, a material optimization is probably needed (both playing
with In or with the annealings). Recommendation is to consider a low In content
447GST as possible material for 30s (recommendation to be check on off-pitch CD
shrink, based on actual PM2A3).

#5 QTT characterizations on Ihold on
cell rev 7.64 have been shared. Main conclusions are: 1) Ihold change with EDs,
i.e. parasitic resistance (lower for higher EDs, range of change 2.5 uA) 2)
Ihold is lower on upper deck ~1.5 uA 3) Ihold increases during cycling 4) Ihold
is higher on cells with buffer on LWL possibly to high capacitance or different
seasoning (due to higher spike) 4) Ihold is slightly toggled by spike mitigation
voltage of ~1 uA 5) Ihold toggled with ON-IV slope still under investigation.

Wk27/2017 Key message:

#1 DTS rev0 draft has been discussed.
The first DTS rev0 is based on MTS rev0 that considers only a planar shrink of
the cell (and a slight decrease in 2nd cut WSiN thicknesses). DTS
includes the key rows for DT while the part related to dummies and reliability
is still WIP. Scaling projections are then discussed in more detail in the
following points of the agenda. Two comments have been anyway highlighted: 1)
DTS consistency of RWB: 30s DTS includes a higher value of the sigma wrt to 10s/20s
DTS (but aligned to what we have on 10s/20s silicon today) with the same delta
Vt (related to same PM thickness scaling from 20s to 30s). Overall the RWB is
thus reduced wrt 20s DTS. 2) today the voltage drop on parasitics is assumed to
be the same as in 20s but the allowed increase in the connection BL/WL
resistances leads to a higher voltage drop (reported numbers assumed a 60%
scaling of IRST). In both cases, it has been requested to find a consistency
between DTS values.

#2 Window and Ihold scaling from PTX
have been discussed. For what concerns the window, actual analysis allows to
project a +150 mV increase in the window. Anyway, this will be probably traded
with a worse set-ability. A proper balance between gain in window and lost in
set-ability must be discussed/prioritize and then DTS adjusted. Part of the
window gain can come from the different scaling of SD/PM Ith. Follow-up to
complete the analysis adding set-ability impact. Concerning Ihold, a comparison
between PTX and S15 trend charts has been discussed. While Imelt has been shown
to scale of about 7X according with the area factor, the Ihold scaled only by 3X.
Follow-up to segment the scaling due to parasitic increase from the one related
to SD area scaling. Request for simulation to help supporting Ihold scaling
understanding.

#3 Ihold versus ED measurements have
been shared. Since ON-IV is not available on all EDs (only ED2 has cells with
local WL buffer), a dedicated technique based on buffer oscillations has been
used for this measurement on cell with the buffer on global WL. A clear trend
of Ihold with ED is visible in the range of few uA variation between ED0 to ED7
on S15. This range of EDs corresponds to parasitic resistance from 4Kohm to 25
kohm. Follow-ups: 1) to understand capacitive impact on Ihold 2) to investigate
the spike mitigation impact on Ihold 3) elaborate an experimental plan to
better investigate Ihold as a function of: temperature, polarity, IPD, decks,
CR.

#4 Bounce/Vth sigma scaling
projection has been discussed. From SD Vt theory, only thickness and Eg, enery
gap, contribute to Vt sigma. Since we are envisioning a scaling without
thickness change, Vt sigma is supposed to stay at 10s/20s numbers. However a
worsening of process related Eg variability cannot be excluded at this point.
Etch/Seal and external contaminants as well as the cell seasoning can be part
of the picture. Follow-up to define a process sigma pareto.

#5 Silicon status                has been updated. 2nd
lot with 2% In-doped (on SDv12) has been funded and it will be released this
week. Additional lot with In up to 5% to be funded in three weeks. Top WC
lamina trial will be funded in iWW30. Possible 2nd lot with AlO
lamina on SD to be funded, pending WLR discussion of previous lot.

Wk26/2017 Key message:

#1
The working
table shown last meeting has been
updated based on the offline discussions of the week. A level of risk for each
area has been attributed based on technical risk and timeline impact. Higher
risk has been attributed to PM set-ability. Risk comes from the known issue of
CD scaling impact on the set-ability and the envision solution asks for PM
material exploration that is a slow activity. Other risky areas are: Idelivery
due to the impact to design activity, and Ihold due to the unknown scaling law
and potentially the inability to flow the nucleation current into the PM. Other
areas are considered lower risk.

#2 A
first attempt of a segmentation
of In-SD window increase has been
presented. Main messages are: 1) No clear smoking gun about delta Vth increase
for In-doped SD split in full stack array looking at SD only memory effect 2)
QTT does not track array data for window increase with In, 3) a possible PM
change due to change in cross contamination has been also checked through
set-ability metrics and it cannot be related to the window increase. 4)
Possibility cause could be the leakage as player in delta Vth measurement.
Follow up is to check window increase with In-SD on not fired array to minimize
the leakage on B/C cells.

#3 L1D updates on WC lamina top has
been presented. Motivation of the study comes from TD improvement evidence on
past W lamina thickness trials pointing to a possible rule of the lamina/PM
interface on the crystallization. WC has been considered as a way to change
that interface (at this moment only the top lamina). Different W content in WC
has been tried ranging from 10% to 80%. W content has an impact on the DE. 10%
W trial showed PM recess and both 10-20% showed lamina CD reduction. Decision
to try at L3 only W content above 20% even if 20% is considered at risk for
high interface resistance that impact set Vt and its cycling evolution from
past PTX silicon.

#4 SD thickness impact on IRST scaling
has been discussed based on old PTX data. Almost independently from its
thickness, SD presence can change IRST significantly. However, programming
power is not changing, pointing to the same total thermal resistance. Cell
aspect ratio does not change the prog power, suggesting Rth dominated by
parallel of top/bottom resistances and not lateral thermal loss. Follow-up for
TCAD to understand which is the explanation for such a behavior.

#5 ON-IV characterization and Electrodes
resistance metrics have been quickly showed. By measuring at high current
levels the ON-IV, it is possible to extract the resistivities of the electrode
for C (PG4T1) and CN (almost PG1T1) stacks that, in this case, are for both
closed to 3 mOhm cm. Extracted numbers looks pretty consistent with C/CN L0
data. On the other hand, Von is toggled significantly. Follow-up activity is to
investigate rev 7.64 and check for its ON-IV polarity dependence.

Wk25/2017 Key message:

#1
First meeting for “Beyond
10s architecture pathfinding” has been run in ww25. Goal of the team is to
“Develop novel architectures/materials/processes know how that can be used
for foundation of next generation SXP technologies”. The activity will be on three areas: 1)
design and discussion of architecture trials on silicon on available vehicles
(today is s15, in the future it can be s26 or s36); 2) new material integration
through L1D and L3 studies; 3) Device physics characterization/understanding
beyond what is known. The team will work in close connection with 1) JET
meeting for strategy alignment, 2) with 30s material path-findings for new
material screening, 3) DD meeting for device physics understanding. Team is
composed by PI/PVD/Material and cell team members. When and if needed other
process areas team members will be call in (etch, CVD, litho). A preliminary
draft table of the activity has also been shared. It will be a working document
to track and define the priorities of silicon activity.

#2
Lot 9897742.003
with AlO/SD laminas probe data have been reviewed. Lot contained different
trials: SDv12 (POR) vs SDv4. On SDv12 there are trials on airbreak and purge,
while on SDv4 there is one trial with AlO laminas and co-sputter trials of AlO
into SD (1%, 1.5% and 2%). Main messages are: 1) Airbreak and “purge” on SDv12:
no toggle. 2) SDv4 vs SDv12: SDv4 shows an increase of the SET median and SET
sigma (+12mV normalized with the median SET increase), but a better uniformity
of the SET median along wafer radius (visible on both decks, in particular on
D0); map is related to co-sputter deposition. 3) AlO lamina shows an increase
of the deltaVT (+145mV; +128mV) and an improvement of the E1 and E3 margin, but
a worsening of the SETsigma (+20mV, on top of v4 degradation), drift and E1
knee. 4) AlOx cosputtering: FF not measurable because out of tested range. The
1% cosputtering is almost aligned with the AlO lamina trial (only drift is
better). No other improvement by increasing the AlO percentage, but many
worsening on sigma, knee, drift, margin. Recommendation 1) run WLR (Anna to
check); 2) run array characterization on s26 SD-only AlO lot to confirm the FS
behavior (Enzo/Mario).

#3 In-SD
drift learning has been shared. Main benefit of In-SD is an increase of the
median window. Drift is faster for short time and slower at longer time.
Overall drift is neutral at 85C – 48h. Trial remains of big interest for window
gain. Recommendation to: 1) segment the median window increase origin (PM
composition change, SD memory effect, SD Ith change) 2) design a new SWR for a
follow-up lot.

#4 In-SD
L1D/PFA and follow-up plan has been discussed. In-doped SD shows higher
impact of voids. L1D activity showed 1) 2% of In can be etch with standard SiH4
chemistry. For higher percentages, SiH4 cannot be employed due to residuals on
the flat etched areas. SO2 has been used instead but resulting in a tapered SD
profile and some undercut below ME. EDX showed In presence in SD for both bake
experiments without In directly co-sputtered in SD and nobake plus In
co-sputtering, suggesting a possible bake role in cross-contamination (In going
from PM to SD during bake).  Opens are
anyway on all the trials, so they cannot be related to different etch
chemistries or undercut. Hypothesis are: 1) high Si content in SDv4 2) small
target depo.  First priority is In doped
SDv12 demonstration. Plan is to run In-SDv12 L1D/L3 lots in F4. SWR can be
found in the linked presentation.