Subject: SeDRAM Paper from Xian UniIC Semiconductor
From: "Tomishima, Shigeki" <[email-masked]>
To: "Fetzer, Eric" <[email-masked]>, "Josephson, Doug" <[email-masked]>, "Thammana, Venugopal" <[email-masked]>, "Thomas, Thomas P" <[email-masked]>, "Khare, Surhud" <[email-masked]>, "Duran, Carolyn R" <[email-masked]>, "Bains, Kuljit S" <[email-masked]>, "Isbara, Melik" <[email-masked]>, "Kau, Derchang" <[email-masked]>, "Majhi, Prashant" <[email-masked]>, "Loop, Becky" <[email-masked]>, "Constantine, Anthony M" <[email-masked]>, "Mallik, Debendra" <[email-masked]>
Date: Thu, 11 Nov 2021 03:16:02 +0000

Hello all,

This is the Custom DRAM paper with W2W F2F HBI from A-SSCC (Asian Solid State Circuits Conference).

Which was just published on this Monday (11/08) in Korea.

This is NOT new, but they published the similar paper at IEDM 2020 as well.

Although I attached the presentation slide PDF,

My summary below would be good start to review.

Thank you,

Tomi 

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Tile: A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration

Institute of Microelectronics of the Chinese Academy of Sciences, China; 

University of Science and Technology of China, China; 

Xi'an UniIC Semiconductors, China

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<Concept>

<Bonding Technology>

- 3um F2F W2W HBI

<DRAM Die Architecture>

- 48Gb die view (6 x 8 x 1Gb blocks)

- From Sense Amplifier (SA), directly data is transferred via 3D HBI connection.

- 128 IO per Bank, 8 Banks per 1Gb Block, 48 Bolcks per die = 128 x 8 x 48 = 49152 IOs per die.

128 x 8 x 8 = 8K IO/GB

- 48Gb die size is >800mm2 (PWC 25nm DRAM Process). Each 1Gb block can be diced for the system requirements.

- IO speed is 266Mb/s, 49152 x 266Mb/s = 1596GB/s BW for 48Gb die in total.

- SRAM-like Interface (Close Page policy) with 3.76ns CAS-CAS Delay.

- The 2nd Gen will be 2-DRAM die stack.

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