Subject: RE: Question in DRAM array
From: "Bains, Kuljit S" <[email-masked]>
To: "Kau, Derchang" <[email-masked]>
Date: Mon, 1 Jun 2020 18:14:12 +0000

Hi Derchang,

Attached sheet has # of banks, page size and die capacity.

Bank capacity can be derived from die capacity/# of banks.

On data width, are  you asking for device width or size of internal prefetch?   Size of internal prefetch is same as Burst length * device width.    E.g. DDR5 has x8 with BL16 so internal prefetch is 128 bits.

Rgds,

Kuljit

From: Kau, Derchang <[email-masked]> 
Sent: Monday, June 1, 2020 9:22 AM
To: Bains, Kuljit S <[email-masked]>
Subject: Question in DRAM array

Kuljit,

I have a question on dram array construction.  In table of “Memory tech assessment”,  for each die, what is 
# of bank,
Bank capacity
Page size
Data width

I am seeking a parallel to other 3DXP. For example, ATF32 is 
# of bank            = 32 partitions (band equivalent) 
Bank capacity    = 8Gb/partition
Page size            = 128b
Data width         = 8b

Does my question make sense?  I am seeking to understand the array construct differences between DDR, LPDDR, GDDR and HBM.

Thanks,

/DerChang