Subject: RE: Question in DRAM array
From: "Bains, Kuljit S" <[email-masked]>
To: "Kau, Derchang" <[email-masked]>
Date: Mon, 1 Jun 2020 19:58:30 +0000

LP5 internal prefetch is 256b.   512b(32B) is created by DRAM interleaving between two bank groups.

From: Bains, Kuljit S 
Sent: Monday, June 1, 2020 12:39 PM
To: Kau, Derchang <[email-masked]>
Subject: RE: Question in DRAM array

DRAM’s core timings main limitation is back to back CAS commands (tCCD).  This dictates DRAM core cycle time.

DRAM was not able to keep up with core cycle time so we created bank groups.  Now back to back CAS go to different bank groups to create a 100% stream of data at the channel.

Bursting all 2K from one open page is no longer practical.

LPDDR5 still might be 256b internal prefetch and they maybe doing two back to back reads.  I will need to explore further as did this work 3 years ago.

Rgds,
Kuljit

 

 

From: Kau, Derchang <[email-masked]> 
Sent: Monday, June 1, 2020 11:36 AM
To: Bains, Kuljit S <[email-masked]>
Subject: Re: Question in DRAM array

Thank Kuljit.   I should ask for both.   In fact, I made a wrong assumption of device width = internal prefetch.  

One more question, in the example of LPDDR5, the device width is X16 and internal prefetch is 512b (16·32).   For the page size of 2KB, is there a reason you cannot bust more than 32, say BL up to 1K (=2KB/16b)?

Thanks again.  This is very helpful to me for future discussion.

/DerChang

From: "Bains, Kuljit S" <[email-masked]>
Date: Monday, June 1, 2020 at 11:14 AM
To: "Kau, Derchang" <[email-masked]>
Subject: RE: Question in DRAM array

Hi Derchang,

Attached sheet has # of banks, page size and die capacity.

Bank capacity can be derived from die capacity/# of banks.

On data width, are  you asking for device width or size of internal prefetch?   Size of internal prefetch is same as Burst length * device width.    E.g. DDR5 has x8 with BL16 so internal prefetch is 128 bits.

Rgds,

Kuljit

From: Kau, Derchang <[email-masked]> 
Sent: Monday, June 1, 2020 9:22 AM
To: Bains, Kuljit S <[email-masked]>
Subject: Question in DRAM array

Kuljit,

I have a question on dram array construction.  In table of “Memory tech assessment”,  for each die, what is 
# of bank,
Bank capacity
Page size
Data width

I am seeking a parallel to other 3DXP. For example, ATF32 is 
# of bank            = 32 partitions (band equivalent) 
Bank capacity    = 8Gb/partition
Page size            = 128b
Data width         = 8b

Does my question make sense?  I am seeking to understand the array construct differences between DDR, LPDDR, GDDR and HBM.

Thanks,

/DerChang