Subject: Weekly (Balaji Srinivasan) WW50
From: "Srinivasan, Balaji" <[email-masked]>
To: "Taub, Mase J" <[email-masked]>, "Guliani, Sandeep" <[email-masked]>, "Kau, Derchang" <[email-masked]>, "Waller, Ken" <[email-masked]>, "Monasa, Saad P" <[email-masked]>, "Arendt, Kevin E" <[email-masked]>, "Friessen, Brian W" <[email-masked]>, "Goldman, Matthew" <[email-masked]>, "Flores, Eddie" <[email-masked]>, "Hasnat, Khaled" <[email-masked]>, "Hill, Ervin T" <[email-masked]>, "Srinivasan, Balaji" <[email-masked]>
Date: Tue, 15 Dec 2020 23:02:51 +0000

2Kx4K 3DxP

Die/Tile CMOS Gap to Goal:
WW51 based on ideas looked at so far.
Tile CMOS fit under Tile Array gap to goal: 14.4 % 
Die size based on this tile area: 105 mm^2
Key enabler is new ROW Mux circuit architecture sharing global select/de devices between deck decoders – W0/W1 – reducing combined decoder height my ~60L and thus die size  
Estimate is Excel calculation based, Route ability is WIP
Prior WW46 based on ideas looked at so far.
Tile CMOS fit under Tile Array gap to goal: 19.1 % 
Die size based on this tile area: 108.3 mm^2 
 
First Pass layout of Tile is in progress, (All: Balaji/Ken/Kevin/Sandeep/Mase/Eddie/Eric/Steve/David)
Goal: fit CMOS under array, and routable tile? – wip, don’t know the answers yet. No showstoppers
P1250 Technology: (2X4K Decoder DR + Non Pitch-cell array DR + M1/2/3 @ 2.12L, M4/5 @ 1.06L)
Key learnings so far:
Consolidation of like circuits is desirable, 
Consolidation of tile logic in S & C  quadrants ( remember ASTC- All, Sin, Tan, Cos ) to minimize routing between S & C quadrants as they take up routes.
Colmux has no polybreak/socket unlike ATF. Track count is comparable to ATF counts.
Rowmux has shared globals between decks and inverters placed all sockets, between/sides of the decoder: it fits the socket. The track counts are comparable to ATF per pitch cell. It needs 8 HNREG switches/tile.
 
No Shift Tile architecture: Ken presented the basis for no shift architecture without.
It provides consolidation of tile logic,  fewer copies of IREF/BLVDM mux etc per paritition, translating into die size, but the energy tradeoff remains.
As it stands, there is a 2+pJ energy penalty to implement it and we are looking for ways to mitigate this to move the architecture forward.
 
Other Notables
GIDL/Rel. – Design to provide feedback to CMOS team based on measured gaps to goals. WIP
Metal Stack: Option1: Eddie/Steve layout analysis shows Option 1 ( M1 @ 2.12L M2/3 @ 1.696L, M4/5 @ 1.06L ) would need M1 @ 1.696L as well to realize 4 track/pitch cell gains for M2/3
Not POR today: this is just a what if analysis to trigger if POR (See above fails )
Current Delivery calculator updated for all iRD/iRST based on current.
Key notable bein 50uA iRST supported by TD ( not 62uA before )

4Kx4K BiSM

Die size and energy 4kx4K @ 33.5
3T Decoder:
Support for 40uA iRST Yes. (Centered 85/TT/Nom Array/Nom CMOS.
Diffusion limited decoder: with added metal support beyond P1241 – Area is 1.12X of ATF rowmux
Routing enabled decoder: with P1241 metal stack is 2.12X of ATF rowmux à 225mm^2 die

 

Fig 1: 2Kx4K 3DxP