Subject: FW: TSMC 5 nm First Looks Rev 2
From: "Majhi, Prashant" <[email-masked]>
To: "Sharma, Abhishek A" <[email-masked]>, "Kau, Derchang" <[email-masked]>
Date: Mon, 21 Dec 2020 19:00:43 +0000

From: Saha, Sayan <[email-masked]> 
Sent: Friday, December 18, 2020 3:38 PM
Subject: TSMC 5 nm First Looks Rev 2

Hello,

Please find rev2 of First Looks report attached with this email. The summary of findings are below.

Die size is 86.9 mm2 (without frame), 88.8 mm2 (with frame)
16MB of LLC, 8 MB of L2 for Big Core, 4 MB of L2 for small core (all 111 HD ~0.0214 um2). HC, TPRF and  ROM also found
Floorplan analysis for digital FUBs show 2 big cores, 4 small cores, 4GPU cores, 16 NPU cores and 4 Performance Controller cores. AMX and Sense HUB FUBs are potentially identified
Poly pitch 51 nm. No diffusion break in random logic area. Electrical isolation done using gate tie down
PMOS uses SiGe channel
Metal gate stack was cut after the gate stack formation
H210 used everywhere
COAG enabled. COAG is used extensively
VCX power rail, made of W
TCN is Co. ViaT is W (need to be verified). Gate contact is W
VCT is CVD deposited using selective W process, which is liner barrier less. This is similar to TSMC 7 nm 2nd generation. VC power rail has Ti/TiN liner/barrier. The W deposition seems like conventional CVD
Total 15 Cu + 1 Al 
H210 has 5 M0 signal tracks at a pitch 28 nm (EUV patterned with SALELE)
M1 is EUV patterned with 34 nm pitch
M2 is EUV patterned with 35 nm pitch
Via0, Via1 and Via2 are EUV patterned
M3 and M4 are SALELE patterned using 193i
Co cladding used for EM mitigation for up to M4
Co cap is not uniform across the line
Metal and Via layers have Ta based liner/barrier with weak N signal. The thickness of these liner/barriers for at least some layers are less than that in N7. Barrier is slightly thicker at bottom than sidewall
M5 is SP with 78 nm pitch
ILD and Etch Stop layers are similar to N7. The same tri-layer etch stop AlN+ SiOC + AlxOy is used
Standard cell library findings show very dense cells indicating WM ~1
Weighted raw density shows ~1.7x improvement from 1st generation TSMC 7 nm process
SRAM fin shows variable fin pitch (similar to previous generations). BL is still at M0 and WL is still at M1. Bit cell height shrink came from neighboring cell PD/PG – PD/PG distance reduction
All of the major IPs like CPU, GPU, NPU are lumped power gated
PDN analysis in big CPU core shows grid design in odd metal layers and staples in every even layers with a lot of additional opportunistic staples. M4 seems to be low on utilization of routable wires and high on power staples
USB and GPIO area investigation shows thick gate long channel devices with 140 nm and 170 PP. The gate pitches are shrunk from previous generation significantly. The GOX has been reduced to ~2.3 nm from 3.3 nm seen in N7 and older nodes
Floorplan analysis was completed with area measurements for all the digital FUBs
The efficiencies for memory macros for L2, LLC and big core are calculated

This is the last “First Looks” report that this distribution list will be receiving on Apple A14 and TSMC 5 nm. Our work will continue on TSMC 5 nm. We will be doing a lot more deep dives in to individual areas of interest and will be sharing findings with relevant stakeholders.

Thanks,

Sayan