Subject: RE: Apple MAcBook Pro M1-Pro and M1-Max teardown report update
From: "Wong, Stephen1" <[email-masked]>
To: "DeBonis, Thomas J" <[email-masked]>, "Goldsmith, Michael" <[email-masked]>
Cc: "Wang, Franklin" <[email-masked]>
Date: Wed, 9 Mar 2022 15:35:36 -0800

Hi Tom,

Yes, I agree. It’s definitely doable based on the D2D specs out there now. I’m guessing that Apple is using a proprietary link but it’s should be achievable. Do you know someone who would have more inside into the IP aspects of the D2D IP?

Thanks,

Stephen

From: DeBonis, Thomas J <[email-masked]>
Sent: Wednesday, March 9, 2022 5:15 PM
To: Goldsmith, Michael <[email-masked]>; Wong, Stephen1 <[email-masked]>
Cc: Wang, Franklin <[email-masked]>
Subject: RE: Apple MAcBook Pro M1-Pro and M1-Max teardown report update

Thanks!  So in short, the Ultra interface specs (3.3Gbps/wire PAIR, 140 GBps/mm shoreline and 140 GBps/mm2 areal are in the ballpark of low-end UCIe) so Apple should have headroom to bump up the speed several-fold when they need to increase performance and yes, the 2x18mm bridge would be a challenge to handle.  They could make it in 1RDL layer at 0.5um L/S + the pad layer, similar to Xylinx CoWoS-S

It will be interesting to see what your benchmark data says.

From: Goldsmith, Michael <[email-masked]<mailto:[email-masked]>>
Sent: Wednesday, March 9, 2022 2:17 PM
To: DeBonis, Thomas J <[email-masked]<mailto:[email-masked]>>; Wong, Stephen1 <[email-masked]<mailto:[email-masked]>>
Cc: Wang, Franklin <[email-masked]<mailto:[email-masked]>>
Subject: RE: Apple MAcBook Pro M1-Pro and M1-Max teardown report update

Sorry, I don’t have that data (for generic EmIB).  You could look at the published AIB spec which describes our shipping use of EmIB in PSG products, but I don’t know if SPR for example drives their d2d any more aggressively than these specs.

https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/accelerating-innovation-through-aib-whitepaper.pdf

We also announced an AIB 2.0 draft spec: https://chipsalliance.org/announcement/2020/07/16/aib-2-0-draft-specification/ before announcing the recent UCIe spec (formerly CXi) https://www.anandtech.com/show/17288/universal-chiplet-interconnect-express-ucie-announced-setting-standards-for-the-chiplet-ecosystem

Copying Stephen who may have a better data reference for comparing this interface.  IMO what is novel here is that the interface appears to be the full length of the shoreline.  It is grouped in banks, and as was observed form the initial M1Max teardown, it is designed to be 180degree abutted, but it is continuous (and so the Bridge IC also will likely be continuous).  For SPR, we have multiple bridge chips connecting the dice (three on one shoreline, and two on the other), because there is a maximum size of the bridge IC that can be supported, which is clearly smaller than what Apple have implemented here.

Thanks

-Mike

From: DeBonis, Thomas J <[email-masked]<mailto:[email-masked]>>
Sent: Wednesday, March 09, 2022 12:32 PM
To: Goldsmith, Michael <[email-masked]<mailto:[email-masked]>>
Cc: Wang, Franklin <[email-masked]<mailto:[email-masked]>>
Subject: RE: Apple MAcBook Pro M1-Pro and M1-Max teardown report update

how does the interface spec compare to EMIB?

From: Goldsmith, Michael <[email-masked]<mailto:[email-masked]>>
Sent: Tuesday, March 8, 2022 8:04 PM
To: DeBonis, Thomas J <[email-masked]<mailto:[email-masked]>>
Cc: Wang, Franklin <[email-masked]<mailto:[email-masked]>>
Subject: Re: Apple MAcBook Pro M1-Pro and M1-Max teardown report update

Yes, clear enough. They state clearly in their foil a "silicon interposer", but not explicitly a bridge or full sized (which I agree the former is more likely).  Might be worth highlighting that part in support of the InFO-L assumption.

Thanks!

-Mike

  _____

From: DeBonis, Thomas J <[email-masked]<mailto:[email-masked]>>
Sent: Tuesday, March 8, 2022 9:47:22 PM
To: Goldsmith, Michael <[email-masked]<mailto:[email-masked]>>
Cc: Wang, Franklin <[email-masked]<mailto:[email-masked]>>
Subject: Re: Apple MAcBook Pro M1-Pro and M1-Max teardown report update

That matches pretty closely with my analysis.  Good reference comparing to DDR Mike but since it’s on silicon instead of widely varied trace lengths getting to an LPDDR on substrate I imagine it’s “easy” to bump up the speed a bit

Is the slide below clear and correct?  Please recommend edits

Thanks!

   On Mar 8, 2022, at 6:59 PM, Goldsmith, Michael <[email-masked]<mailto:[email-masked]>> wrote:

   So based on the ~756B wide interface, if they run that at 3.2 GHz (aligned to the LP5-6400 refclk), they would get 2.4TBps, which is pretty close to the 2.5 claim from today.  Maybe they are running a bit faster than 3.2 GHz on these PHYs. LP5-6400 * 8 interfaces at 128 also exceeds 800GBps (819.2 GBps exactly).

   Thanks

   -Mike

   From: DeBonis, Thomas J <[email-masked]<mailto:[email-masked]>>
   Sent: Tuesday, March 01, 2022 2:45 PM
   To: ATTD Competitive Analysis <[email-masked]<mailto:[email-masked]>>
   Subject: Apple MAcBook Pro M1-Pro and M1-Max teardown report update

   Attached please find the update to our teardown report on the Apple MacBook Pro featuring the M1-Pro and M1-Max SOC. This update includes additional 3D xrays, materials analyses, 8 and 16GB DRAM assessments, and other data not included in the first revision of the report.

   Since the M1 Pro die is a simple chop of the M1 Max and they share packaging materials, etc.  Data duplication has been minimized.

   *    The M1-Max SoC is comprised of a 19.04 x 22.02mm (419mm2)die on 35.7 x 56.8mm  310um thick 11-layer coreless ETS substrate.  M1 Pro: 19.04x13.3 die/ 24.7x56.8mm substrate.

      * 11-layer coreless ETS substrate, e-less NiPdAu cap on surface layers (pads, dams 2DID mark). No solder resist on FLI side. Assembly may have been done in strip format.
      * Unique girdle shaped Cu pillar bumps at 85 min pitch with Sn (so SnCu) FLI solder, landing on e-less NiPdAu substrate pads .
      * Cu layer thickness ranges from 8-15um. Dielectric layer thickness ranges from 10-18um except ~25um thick due to glass cloth in 2 layers closest to board.
      * Min Line/Space observed is 15/12um single ended routing, 20/35um for differential pairs. 100um round adhesion holes versus the square grid hole pattern used on the M1 and A12X.
      * Substrate and board 3D X-Ray imagery is included.  Contact ATTD C/A for access to the full high-resolution images.

   *    The MacBook Pro 14” M1-Pro and –Max are built on a 1.1mm thick, 16-layer Type 4 PCB. With exception of more robust RF shielding, construction is typical of MacBook Pros..
   *    The M1 Max SoC die is ready for ~770 IO/mm die-to-die interconnect using 25um minimum pitch InFO-L (silicon bridge embedded in fan out RDL interposer) or similar advanced package technology.  A high-density differential IO circuit block along one edge of the SoC was not shown in Apple’s press releases.  This block is currently populated only with power/ground bumps (at 140um bp) but can provide 756 bytes of die-to-die data transfer (770 IO/mm escape density, not including P/G reference etc.) when connected on a fan out embedded bridge interposer at 25x35um micro-bump pitch, consistent with TSMC’s disclosures on InFO-L design rules.
   *    Similar to M1 MacBook, thermals are managed with a dual-fan cooled heat pipe which penetrates the heat sink to directly contact  gray TIM2 (triauryl phosphate  with 9um Al and ZnO filler) above the  Ni-plated Cu IHS.  A black grease-like TIM2 (PDMS with 60um AlOx particles) fills the gap between DRAM packages and the heat sink.. The same grease-like TIM fills the gap between the bottom-side VR components and the EMI shielding.  TIM1 is PDMS based, with Al, Si and traces of Zn in filler.  PDMS based sealant with Al/Si filler holds it together.
   *    As mounted on the PCB, the IHS has 72um convex warpage (frowny face) and BGA heights range from 190um to 390um indicating the substrate, stiffener, and IHS combination was marginal and would not meet industry’s JEDEC expectations. DFM and reliability was obviously considered when planning the ball map.

      * Warpage is managed with a ~1.3/2mm wide 0.4mm thick nickel-plated stainless steel (Fe/Cr/Mn) stiffener ring around the substrate perimeter with a ~flat plate IHS adhered to the ring. The IHS has cutouts for the LPDDR packages; both 8GB and 16GB DRAMs extend up into the hole, but not above the IHS. DRAMs were attached before stiffener ring covered key fiducials.  Assembly was possibly done in strips to support tight stiffener-edge tolerance and manage the in-process warpage.  Fiducials near the substrate corners were not noted for stiffener attach.

   *    14x14mm (2406 BGAs at 0.27mm) LPDDR5 packages  (Max- 4 pcs, Pro – 2 pcs) are SMT’d to the top of the substrate and underfilled before stiffener ring attach. Our teardown samples had either Samsung 8GB (1Gb 1-y die, 0.65mm Z) or SKHynix 16GB (1-y die, 0.85mm Z).  Both suppliers used a 4-layer (coreless/prepreg dielectric) FBGA package.
   *    M1-Max Power delivery is managed with 3-5 CMOS voltage regulators with integrated magnetic inductor power delivery ICs attached to the other side of the main board directly beneath the SOC chip. 34 DTCs and 17 IDCs on 5 CMOS voltage regulator with integrated magnetic inductor IC’s are mounted to the board directly beneath the SOC. 10 0.5um thick Cobalt-rich (CZT?) sheets above and below 18um thick copper traces form 28 integrated inductor pairs on the 4.6x5.9mm die.  They are attached as 6.8x7.4mm 4-layer coreless exposed die CSP packages with ~0.5mm BGA pitch/BLUF.  (3 components on M1-Pro skus). Across the Mi-Pro and M1-Mac there appear to be 5 variants of voltage regulator packages.  Each component can support 2 power rails.  34 ~1.7 x 2.3 mm 100um thick / 9um Deep Trench Capacitors are SMT’d on the substrate land side (140um bump pitch).  These may be a new design; DTCs used as LSCs on the M1 package had 30um trench depth, embedded caps had 6.8um depth.   Additionally, 17 0603 3T Die Side Capacitors are used.

   All ATTD Competitive Analysis publications – including higher res PDF version of this  tear downs and TechSearch, Prismark, Yole reports, and more are available at ATTD Competitive Analysis on Microsoft TEAMS or intel.sharepoint.com.  To get access, enter code 8hchhg2 at the very bottom of your teams list where it says ‘Join or create a team’.   After you’ve joined you’ll be able to quickly access the home page from your browser.

   Please note: As a member of the ATTD Competitive Analysis PDL, you will continue to receive all new documents by direct email.  Please contact Tom DeBonis ([email-masked]<mailto:[email-masked]>) or Jose Perez ([email-masked]<mailto:[email-masked]>)  to be added to or removed from the ATTD Competitive Analysis distribution list.