Ohh, let's 505.
OK.
Well, you're like, he's complaining.
This is too generic over I don't, but you know, please ask
questions.
We can dive into anything you want and yeah, here is what I I
prepared for today.
The transition from Finfets to get around and in terms of
Nanoribbon and a friend sound is OK.
Online bots online the the voice is OK.
Yeah, that's perfect.
OK, great.
OK, so I I think every company has to have their own name like
multi Bridge something right or or remember the try gates,
right.
So yeah, I think that's fine.
So little bit about transistors and interconnects and and you
know the bigger picture and something about cryogenic
operation.
Uh.
For you to think about, OK, but we can dive into any topics if
you want.
So here I just want to start with variability and emphasize
that it's important.
For example, here the histogram of your say driving strengths
into distribution on a wafer.
And suppose you have a technology a like this and
technology B that has like better nominal performance but
more variability.
The problem is that is that for the circuit to work, it has to
work at at slow corner which is minus 3 Sigma.
So if that that variability is is significantly wider, there
might be no reason I mean no gain in in having higher nominal
performance, right, you know the the way they're variability just
takes it back.
So it's important then, uh, of course you want it to be 0, but
it's never zero.
That's so I the foundry, the fab is trying to reduce it as much
as possible, but uh, we get what we get.
And my point here is that some often we see variability as the
driving force.
Uh.
I behind switching from one transistor architecture to the
next.
What you see here is Sigma Vt for minimum size transistor
which is makes it basically a SRAM centric right and asram is
more uh you know sensitive to variability anyway and here is
timeline that's like 20 years ago, right.
And that's a few years ahead.
So what we see here is solid lines are silicon data public
silicon data.
That's from coming from Sanjay, and that's TSMC publications.
And then the other lines show the at underlying mechanism,
variability mechanisms, random doping fluctuations.
I came at all gate.
Uh, and then some other will will come in.
So for planner what you see it was getting worse and worse and
worse because of random dobens.
Uh, and there's just nothing you can do about it, right?
As you scale your size, Keira lustration, source drain and
some you know percolation current, getting through this
field of Arlington opens, so the interface introducing Finfets
was like a reset button.
The first one here, 22 nanometer into FinFET, was just little bit
down, but then eventually it was quite a bit down and that's like
1416.
So it was really good at 7 in the meter and from there it
started deteriorating because squeezing more.
Uh, in those scaling uh.
Was increasing variability.
So so geometry now is is the the main variability factor.
High chemical gate people learn how to do a Morphos.
Uh, your function layers and then it basically disappeared.
So going from three to two nanometer, if you do, if you
stay within fats, it starts to get into bad territory again.
So for example, if you look at TSMC and and even they introduce
and gate all around beach, I think they did reluctantly.
There's a reason I think that's the reason you know that the
gate around has much tighter variability, mostly because you
go from Lisa H definition of the of the of the thin.
Even with spacer, it's still not perfect and we will look at the
numbers there to get all around where the the critical size is
determined by epitaxy, which is much more precise.
It's like 1 monolayer plus minus any questions on that one?
Why do you have the merged?
The point between the infant and the gate around then start
diverse this one.
This is still thin fat good.
This is still be thin fat.
Get there, right?
Yeah.
Yeah, I see.
Yeah.
It's like, yeah, here, if in fact starts, you know, 22 for
Intel and and, you know, 1614 for everybody else.
But here, that's the the first gate around here the the sweet
spot.
Or the optimal before inflection for FinFET was, you said this is
70.
The FinFET, yeah.
Yeah, the right seven was the.
Yeah.
Then they Terra and when when you say geometry, what that mean
is the invites and channel lengths and I'll show some
example.
OK.
And the GA help them with yes, exactly.
Well, the critical size, it's, it's this thickness.
It's like more like finviz.
If you look at film pad, but yeah, it's the critical size
that's the most important.
Basically, Edge versus deposit control app.
Yeah, yeah.
How do you think the number of sheet will have impact on the
Sigma like more sheets is gonna lead to better?
Usually.
Usually it itself, courage is more.
Yeah, in averages more, right?
Yeah, you have some self average.
Yeah.
So so yeah, this this is silicon data that's published.
You know all these numbers.
So that's like, yeah, observation.
And here's here's an example.
That's we took seven and a meter technology.
Get some scene in this case take insides, uh, and you can tell
you more about that company that was spare time.
So they they do analysis of different technologies and and
for this one there was 65 Harris solution images where you can
see every atom in the in the channel you see the channel is
is crystal silicon.
So you can see every atom there.
You know these these things are more full, so they are more
blurry.
So you can really accurately measure the sizes and and that's
the distribution.
This histogram is what we measure, and then you extract a
statistical distribution there and you see that you know .37 is
the number I was getting from SFML.
People, they say, you know our our immersion leather gives you
points 37 one Sigma well, the measure more like .9.
So could be edge adding something or whatever else, but
basically when you have final fee and it's more like .9 and
you can see it, you know image over skinny one and A and a
white one.
No.
Are you showing the range the image is showing from the seven
nanometer you're seeing the lowest low with bin and then you
see the variable.
What?
What I believe in that sample was going from 3 to almost
seven.
Yeah.
So this is like 7 and this is like 3 and everything is 5 1/2.
I see.
I think since then like at 5 and 3 millimeter, they must start it
down a little bit closer to five the average, but the variation
they see is not that much different.
And then if you look at the so here was was a lot of data and I
think this long tail came from define five feet design some uh
like patterns sensitivity.
But you know, if you remove those five thin cases, then you
found that the total Sigma is .7 for the film weeds and the local
is .6.
So most of it is local and here is example of top view channels
in esram.
There's quite a bit of variation.
That's like pair pairs of the things on the same same image
thing.
One thing two.
So if there was systematic dependence, it would be, you
know, crowding along this line.
But it's more uh, logic cloud and and efram cloud pretty
random.
So that's what we extracted and when we plug in these these
numbers that we extract from images into our tools, we get
exactly the, you know electrical variability numbers that are
reported here.
So here is the first production gate all around.
Technology probably so these images what is nice here is yes,
pretty tight distribution.
Nothing like we had for the film from 3 to 7 nanometer, right?
Yeah.
Nice.
And it's hard to get statistical numbers though.
I mean, you have three.
So not here.
Yeah.
Well, we actually we got some statistics working with applied
and IBM and they measured large large samples and found you
know, 3 Sigma is like .1 something you know like quarter
of magnitude less.
For getting around.
Uh, some of the tricky parts for getting around is inner spacer
is 1.
Tricky.
Uh, new step right, for example, when you have the silicon and
silicon germanium and then you remove silicon, germanium
sacrificial silicon, germanium umm based on germanium content,
there is some intermixing going on.
So you have these funky shapes, for example.
That's the uh, you know, they remain in silicon germanium
there that will be removed later like like this part when you do
replacement gate.
So you have some funky shapes for high cameral gate for
example like that.
Makes sense?
Uh then?
Where where?
Where do you?
Where do you get that tip?
I guess there's intermixing, but how are you getting that tip?
Well, because of the it's more or less isotropic agent, so you
start from from here and you start from there and you have
Yeah.
these two things coming from the sides.
So the the center gets less time exposed to the chemistry.
If you keep patching more then it will get more straight away
eventually, but then then yeah.
Hmm.
Yeah.
Yeah, I I would think the center of would actually start and you
would have kind of a, I mean it's it's not a, it's not a wet
affect.
There's no surface tension or anything because it's chemical.
OK.
I I would have expected the other way, more like a smile
rather than a tip.
That's the top view.
That kind of like the the vertical profile, right that you
Yeah.
That, yeah, there's a like Half Moon here.
see on the right is more like a smile, you know? Umm.
Yeah.
Well, I don't know if you have those images in your team.
Haven't seen those objections and the this is the the left
Yeah.
picture is from the tool right tool suggests that profile that
pictures like this.
Yeah, yeah, yeah.
They they the model.
So what is the underlying physics for just face etching
with germanium?
Uh.
Content as the H rate you know trigger, so it's a bug behavior.
Yeah, yeah, yeah. It's another.
Anything to do with the surface?
No, it's bulb.
It's bulk.
Plus I I isotropic edge, you know, because this part gets
exposed earlier than the center part because you have to get
through.
You know that that area?
Yeah, that's what I was thinking.
That or dear friend, is a kind of speculation should be like a
smile or something, and even not as well.
You see chemical load?
No, no, it's OK if you if you if you're initial starting point
was here then I would get a smile.
But it's not because you have your silicon germanium there,
right, so you start teaching it, you start from this side.
You start from that side, so you get like you cut it off here a
little bit before you get to the middle.
You see, that's why.
Because there's extension there.
OK.
And then the AP.
So what we see here?
Let's see, this is Silicon channel.
So let me come come to that page here for a minute.
I'm going to get the I, Anil. She desola.
Uh-huh.
What am I supposed to do to do the cross section?
Should I cross section certain location so I can get the
sensitivity, therefore one and start doing the yield
engineering or performance improvement?
I can take this picture better and say hey, take it out.
You guys go fix this?
Yeah, it's tricky because when you do sample for TM, it has
certain thickness.
Several, you know, 10s of nanometers.
So what you see is a average no.
Some thickness.
So if it's a tiny thing, it's gonna be, you know, not visible.
OK.
There. Got it.
OK.
Maybe top view would tell you something if you have several of
these things repeating over and over, right?
Right, right.
So right.
OK, I don't know if you can do top view TM though.
No, we talk about that is probably just a atomic size,
right that.
Yeah.
There there.
There's really no way to see this.
Maybe you know what KLA would do is they would actually run this
model like this and do an optical model and see if you
have that tip or not.
That's that's what I think KLA would would be doing.
It would be using this type of model generation like you have
on the left and then seeing what it would look like optically.
And the manifestation this electrically is a Sigma.
No, that would be systematic shift.
You know it's it's just that like channel length here is
short and here is Long and here is short again.
So you have like OK variable channel lengths in the same
manner ribbon.
I see.
OK, good.
So so here we get to the AP.
That's a channel.
That's a channel and this is silicon germanium sacrificial
that's in their spacer and then you are growing silicon
germanium source drain for PMOS, right?
So part of it comes from the wafer.
You know, some pieces come from these channels, so you see lots
of dislocation like second folds there, right, which is typical.
And when we do this atomistic, latest kinetic Monte Carlo, we
see we see how these these things come together and start,
you know, taking folds.
So basically the the problem here is that you have several
seats surfaces like like here and here and you have something
growing from 1 something from another.
But these two seed surfaces are somewhat deformed with respect
to each other because of patterning, and perfections,
slight deformation, and if you have like fraction of an
industrial deformation then when they join the next item is
confused.
Where do I sit?
And that's that's how you get this location one, you know,
evidence of this is, is, is is here.
Here what we have is silicon growing on silicon.
No intentional stress.
Not even silicon germanium right?
And initially everything fine, but then you see this signature
of double patterning like narrow, wide, narrow wide, you
know, shallow, deep.
And when they come together, same thing, stake and folds.
Uh, so basically it's it's this themes being deformed
differently by, you know, push pull from STI and stuff like
that, Several seat surfaces trouble.
Once it's surface, you're fine.
So in the FinFET, you etch away this, this you know cavity
before the AP and then you grow it.
Even if this one and this one are somewhat deformed, you grow
it one atom at a time.
You know, attaching here and as you grow it, it corrects,
corrects, corrects itself.
And then you know becomes effect free.
So singles seat surface is the key.
For example, here I think what they do, there's no inner
spacer, which is really bad for parasitic capacitance right
between the gate and the drain.
So I think what they do is they keep your initial silicon like
that.
So you have a single surface and then you're fine.
Well, except for these voids, but at least knows taken folds,
so you can get either stress or or inner spacer.
Pick your poison.
And I I think the way to go here for for that particular thing is
to not try to merge all these source and drain, keep some
space there and deposit metal with stress.
Apparently ruthenium can be compressive and tungsten or
something like that can be tensile for inmos and you can
have it both ways.
Metal insertion with stress.
OK.
Then for transistor I just wanted to emphasize that if you
look at gate-all-around, it's mostly, you know, playing on the
side outside of SRAM where it has to be as narrow as possible.
Uh, so all the behavior is similar to FinFET.
And when people say that's a better electrostatic control,
this this you know, the four stage doesn't give you much.
It is better if pathetic control because you you have tighter
thickness control.
That's why so you're slow.
Slow in fast corners at you know.
Close it together.
That's that's the main thing.
And interesting thing about modeling one of the trends we
see as the industry scaling things then the ballistic ratio,
meaning how many electrons and holes get from source to drain
without any scattering events is increasing.
It's in this 70 something percent now.
Ohh so one side effect is that the transport is determined by
fundamental you know material properties not by specific fab
surface treatment or stuff like that.
So long time ago that was the main thing.
You know, how is your surface prepared?
So for modeling you would need a lot of calibration to specific
fab, but now everybody is the same, just based on the material
properties.
And modeling gets more accurate and good. Then yeah.
Predictable, right?
Yeah, exactly.
It's not depending on the process, it's exactly trails.
Yeah.
So actually when we got some first data from industry
partners on on nanowires, it was surprisingly accurate because
it's there is, that's good ballistic.
It's like no scattering.
Yeah.
Get the most out.
Ohh it's a reliability become like lower team.
No, no, because you could collate Andy, she much faster.
No, it doesn't have enough time to to to be to energetic like
hot carriers in mean anything energetic carrier hungrier.
No, with they were not actually.
Mobility is, if you think in terms of mobility, it's lower as
as you go shorter because it doesn't have time to accelerate.
Ohh the transient call it like politic mobility, right?
Which is not the mobility.
Yeah.
So one other interesting thing we do here is we look at the key
for thin, you know, piece of silicon as we scale it.
So silicon thickness is scaled here, right?
And here is indication of different technology nodes one
and it's undoped and we keep everything fixed.
Channel lengths.
You know the metal gate stack and we use quantum transport to
get it right.
So 1 interesting thing you see is that your Vt is increasing
both within and, which is sad, which is not intuitive.
I think less silicon, easier to invert.
No.
Why not the cause as you thin it down, the the band gap gets
wider.
Remember, single atom doesn't have bands that has like levels.
When you put a lot of items together, those those levels
splitting the bands, but when you have only few items
remaining you have less smaller bands and bigger gaps in
between.
So it's more difficult to invert thin silicon than thick one.
That's one observation.
Another is that you know, once you get below like four 3 1/2,
it gets too steep.
If you're variability, you know here gives you plus minus
whatever 40 milliwatt per one nanometer.
There it it like 300 milliwatt.
So you don't want to go there because of variability,.
In the much below 4 nanometers.
Now if you look at transport and here this is a current as a
function of the same silicon thickness.
Again, we keep everything fixed.
It improves and then drops.
Uh.
Even if it's ideally flat surface which never you know
happens.
If you have this, this is like one atom steps up and down
different cases.
Uh aligned and and you know in in counterfeit give you that.
So again, you don't want to go below about four nanometers.
What is right now Gate-all-around is, is that the
range right now it's like or.
Yeah.
If you look at these Samsung thing, yeah, it's it's it's,
it's you.
They jump right away to to form and the meters which we surprise
them, you know, they were able to push right there.
I think what I'm saying is not.
You're not gonna be able to scale it much more, right?
One of the projects we did, I think we found if you're
gate-all-around thickness is 6, it's not competitive to thin
fats.
You have to shrink it at least to five to be competitive.
If you in fact.
Does this change your completion capacitance, no Electron
constant Tony thing?
The patients, not really.
So you did not buy back any other capacitance, lower down
the capacity.
So I think I don't think so.
Yeah.
And then this view is this, that's the channel dimensions
like length and and you know smallest smallest dimension like
invites or or gate-all-around thickness.
So here planner transistors, we were stuck at this location for
long, long time like 25 nanometer channel lengths
because there was this.
Silicon limitation, which was soft limitation on one you know
hand but it was limitation nevertheless.
Remember you to prevent a short channel effects you would dope
the channel, but if you dope the channel too much you you you're
mobility drops so you you pull it back and then you have short
channel effect.
So it was like a balance that would was limited enough at 25
nanometer channel length source to drain junction.
And then Finfets, you know, avoid that as you go below about
14 millimeter film beads, you can you can start scaling it and
FinFET scaled channel lengths, right?
But then the problem is Direct source to the end tunneling.
If you go for silicon for for 3/5 materials, it's like 15
nanometers and germanium, you cannot go below 15 nanometers
for silicon, you get down to 7 to get direct source to drain
tunneling, right?
No, no worries here.
But then as you go below 4, remember you you get two too
much sensitivity both electrostatically and and and
transport drops.
So we are stuck.
We are stuck in this corner.
And yeah, if you go to high mobility, it it only pushes
that, you know, remove that scale in the channel length
scaling.
So you can have it either fast or small.
Transistor stress engineering is interesting it it lets you, you
know, massage your speed along the channel.
And maybe if you use the wrong stress in the opposite in a
transverse direction, you can reduce gate leakage you know and
also increase number of carriers that way.
So stress is an interesting tool in that in that sense you meant
channel with there which channel wall is dimension.
It's it's, it's for the fee and or or thickness for the
gate-all-around.
So 2D material can get you in this territory.
It can be like, you know, one nanometer Fick, right? But.
I'm not sure you want it because when we look at at at this.
Uh, so.
So you look at 2D material and say, uh tungsten Dessel fight
here is here channel and then you have some dielectrics around
it or or you know metals for the contact.
And if we when we work with like iMac to to reproduce their 2D
material experiments, we have to introduce lots of defects to,
to, to, to reproduce what they have.
It's far, far behind silicon now, even if we assume that that
the contacts are, you know, perfect and the the electric has
no interface traps, which is not the case now, but let's assume
it's it's it's it's solved still it's like 2 eggs behind silicon.
And you know the way we do to the material is that if this is
silicon gate-all-around channel with four millimeter of
thickness, then you put maybe two uh strips of 2D material
here just to you know, get more current.
Uh, but The thing is, you know, mobility here cannot be much
larger if it's if it's higher mobility, then you cannot get
short channel lengths.
And once you dial in mobility to the right space to scale, then
it's like silicon.
But then if it's less than a volume then cross section, then
silicon, then you lose current.
So I think the best case we study material is to mimic
silicon, you know, feel this whole space.
But then why do you switch from silicon to 2D material?
Wait, so you're saying the 2D material, essentially due to the
high mobility you have direct junction junction tunneling?
Is that why you can't?
Yeah, any any, high, any famility means Low, smaller
Hmm. Umm.
effective mass and and and you know more tunneling.
Hmm.
Because you're so source, bare becomes so thin that the
carriers get get over it without knowing it.
OK.
And any quantum transport tool will will show you that.
Yeah.
So if it's that obvious, why?
Why is there all this research being done?
I think I met.
To try to make this the next thing, yeah.
I I I told the American 2013 that 3/5 is not gonna happen
Uh-huh.
because of this reason, but they kept juggling it because they
Right, right.
have to attract people.
Until last year, I think they dropped it last year.
Is it?
Is it basically the phenomenon of the research?
People need jobs.
It it's a jobs.
That's one.
But then look at the at the government, the government in a
Yeah.
long time ago said silicon is mature, industry industry will
figure it out.
So the only fund non silicon and then people have to research
some exotic stuff, right?
Maybe.
Maybe I just get some clarification.
The two D material the construct.
Umm what's what's a space in between two of the two?
The two.
The two. Yeah.
Yeah.
Well, here we we keep it at 4 nanometer.
So if if this is like one and this is like you know one then
this is like 2 or something.
So what?
What does that in between it just dielectric?
Yeah, the this yellow is S I/O and then the red is half Yim,
oxide.
Why you want to construct this way?
Why you?
Why don't you want to just a thin it down?
You can.
You can, but then you pay even more price with parasitic gate
to drain capacitance in between.
You know, between kennels, capacitance, remember?
OK, let's let's get to.
Sorry this one.
This is your gait, right?
This is your drain, right?
This is your parasitic capacitance.
Even if you insert inner spacer here, still this is parasitic
capacitance.
If your channel is really thin and carries little like like,
this is like 4 nanometer channel, right?
Yeah, if it film carries little current, then you need more
stack.
You know more than 34510, right?
So you would have little to do that.
Which is the thing that whole stack.
I would just redo the whole stack.
Can you?
Ohh I need just a channel and then one monolayer with a white
Electro and if I want to double up it just do the back back.
OK.
So when it construct then the real challenge is that how can I
do 2 monolayer right one on the later?
I agree with you is is losing losing on capacitance, but you
have a 2 month old layer with the back to back.
Umm, right.
I just reduced the total number of the stack per layer or per
stack of back to back stack.
My capacity is is going to be neutral or even to certain
points.
Advantage, isn't it?
Well, the problem is not capacitance, in this case, but
the the amount of current.
If mobility similar to have similar channel lengths right,
then you know one or two monolayers will will carry much
less than than Silicon 4 nanometers lab at the same
mobility.
You know your channel cross section is less OK, that's the
problem.
So you're driving.
Strength will drop if you do that.
OK.
The other question I have is the the the current drive at the
plot here.
This is I'll simulation.
Yeah.
I mean the silicon seifa is on simulation as well.
Well, silicon is calibrated to whatever silicon we have.
I see.
I see and and and.
This is assuming fixing all this issues so that you insert all
the time.
Just take them away.
Exactly.
Still losing?
Exactly.
It would be interesting to look at that exactly.
Yeah, very good.
Because we want to look at what do we get if all the process
problems it IMEC look at this data I showed them, but they
they have different business they have to you know show
something.
No, no, no.
Look at this.
Look at that.
Go on with all this option potential options right?
So yeah, so and that's it.
Yeah, I'm not against people exploring stuff.
I'm just trying to see what's the gain and we don't see it.
Victor is party pooping.
Basically, no.
No, I don't have an agenda.
Right.
I'm living by data that neutral Flores,.
Yeah, he doesn't have it.
OK.
Actually, if I'm driven by agenda, then I would want you
guys to to run more tools lations and try this.
Try that, but I'm telling you, we don't see much in that
direction.
Wait, so OK, maybe different switch type than than most fat,
you know, maybe.
OK.
So do we construct the 2D runway?
I don't know what's the right way.
Should we do 2D vertical?
You don't think all has other problems?
You know, I might try it for a while.
We tried it.
We we don't see benefit because you know if you if you had like
majority and logic right then it would be beneficial when like
all the sources are that the wafer you only have to contact
drains right.
It might be beneficial there, but that's a, you know, paradigm
change for all fabulous people.
Try try that.
You know, they don't want that.
They want little incremental changes and whenever you need to
get to this to this bottom, you know, like source for secuencial
connection, you lose all your area again.
That's what we found, OK?
Good.
Yeah.
So basically if Lin, fires getting you know slimmer, you
work with the people in the land space and they also looking for
2D.
They're looking for the milk.
Yeah, memory looking for milk.
Meaning the single crystalline channel and they're looking for
2D.
They're looking for 3/5.
Have you talked to them on this type of things?
And they're they're somewhat, yeah.
Yeah.
OK, it will be interesting to see how they view the whole
thing and then use your tool to understand which direction they
need to just wait.
I think they are.
The the whole game is more like fix an imperfections because you
don't get this nice, you know, 120 material, yeah.
More like Poly or some flakes and stuff.
I guess that's the problem they face.
Just going back to two day, what is the?
Obviously, 2DS been talked about for years.
What is the current temperature?
Is there still what is website besides your conclusion?
Temperature.
Resolutely, no.
In terms of uh, the effort spent on put on, yeah, the temperature
in terms of effort and interest that put in CVD.
Yeah.
Should we temperature?
No, no, I meant not.
Not actually, not the temperature, temperature,
temperature.
Also interesting, interesting or the effort people are still
putting in relation temperature, manufacturing temperature?
No, no, it's ohh.
OK.
OK. OK.
Yeah, number of page.
I'm I I I think all foundries are researching that.
Yeah.
So it's still basically, yeah, but if you look at the equipment
manufacturers, they don't have equipment for that.
And that tells you something nice, yeah.
So the the more like modeling and and doing some you know one
off things it's pushing for.
Yeah, it it.
It reminds me of the three, five, all the research work
there is just.
Kind of there.
There was no obvious way to do it, but they just kept
I.
publishing and kept working on it.
Yeah.
And one related thing you probably saw announcement by
TSMC couple years ago that they have Carboni, tubes already for
the like in the in the back on the fly you can put it high in
your you know interconnect and they were suggesting it as the
power switches.
So they're big and they're not trying to compete with silicon,
but they can be power switches.
Right, right.
Some news.
Yeah.
Yeah, OK.
Yeah. Alright.
So yeah, basically slim or slimmer films and then
gate-all-around and then vertical doesn't look promising
because of, you know, serious connection to the materials.
At least I don't see much.
So see fire looks promising, and after that one way to go is like
this.
But then there is no paradigm to connect them.
How to connect?
How even how to think about connecting them together?
I think that's the biggest problem.
Chiplets is easier.
You know you do 2D cheap here to do cheap there you connect them
with a business that's already available in in EDA, yeah.
Interconnect.
So here what we see.
Resistance as a function of the wire cross section area and that
we did with with Applied Materials and presented a couple
years ago.
So power rails copper is clear winner like 2X and that's why
you know everybody's with copper 7 nanometer node.
The signal wires are similar, so still fine, but as you keep
going, you know towards 1 nanometer node then copper
becomes really bad.
Cobalt better maledom or ruthenium ruthenium is similar
to molybdenum, much better mainly because you can etch
molybdenum moral finium so for copper the problem is when you
do the machine narrow trench, small small grains, lots of
scattering these things you deposit everywhere you are new
to be greens and then you etch so you you have small wire, big
wire still big gains same big grains that's that's the
benefit.
So when we actually extract from this data, uh from resistance,
the extract resistivity material property we see formality donum
flat line meaning you know it's it's insensitive to the wire
reads which is the best you can get.
That's perfect.
Because your brains are still big, you first you grow grains
and then you etch.
So it's anyone doing it?
I think cobalt people do in Malibu referendum.
Not yet.
I just remember R&D set up and iMac and I I think it's a
big again change you know to to a subtractive process because
people have everything for the machine.
Yeah.
So just the switches is, you know you have to somehow justify
bigger.
So this data is coming from Applied Materials and material
like all your data is coming from there physical data.
You should like the data that they can show.
Right.
They have data from customers, but they cannot show it right?
And some stuff applied.
Let let's us show.
Now if you look at the you know interconnects like the the metal
zero kind of thing, the beach, the wire beach, the spacing.
And so let's see, three nanometer, you know, we are here
2 nanometer one in the meter or whatever it is, right?
We I think the thing here is that it probably gonna stop, you
know, around 20 nanometer or or or or there and here is 1
interesting way to look at this.
This is resistance of 100 CPP along wire which is kind of
typical for Circuit 50.
Some circuits would be 50 average.
Some circuits would be 100 supplied average, but in this
range.
So when you turn on your transistor, they won't stay
resistance of your transistors, like this.
So alright, all good days.
Your your copper resistance was much less and you are fine.
That's what you want, right?
But as you scale, you know.
Imagine here your wire resistance is worse than your
transistor, so it doesn't deliver your signal.
You don't want to be there now.
Metal Zero is different.
It's very short.
It's never gonna be like 100 CPP, so metal 0 metal one, you
can get away with with with that stuff.
But for routing layers, no.
So I'm just showing, yeah.
This this other one.
Yeah, but for the routing layers you you would need the
flexibility to go wide when you need, right, which then
Right, right.
basically copper is ideal.
Because the maledom would be quite resistive, even wide,
Yep.
Yeah, but but there was never a mean copper.
yeah.
You never anyway use it for here.
You're looking at M0 versus above, right?
Right.
I mean routing is way above right?
Umm.
And then copper, I mean M 0, nobody will use copper because
Yeah.
of the materials property to begin with, right?
Yeah.
And you can see the cobalt and malignant they they they buy you
little bit but not that much, right?
So here Victor.
Alyssa left side chart here and they have the fix aspiration.
In terms of the front section, yeah, that's a different story.
That's whatever you want.
It's it's a capacitance, versus Vasant.
Trade off.
Yeah, you you can play with that.
OK, so I tried to think about how to apply this picture to the
the left the right side picture here.
So right then here you would need to assume some aspect
ratio.
Yeah.
Yeah, that's what I'm saying.
That typically are they 222 to 1.5 to one, I assume 2 to one.
Yes, I see.
Yeah.
Yeah, you're right.
Yeah.
OK, now we try to play with some like seafoods, like transistors,
right?
Say this is a flip flop to double height, meaning that this
is one row.
This is another row double Hide, 4 tracks, you know, 4 tracks
here, 1234 and 1234 tracks there or five track.
So you see, in this case, when you do five track, it didn't
help you to shrink your weeds, so you air is 25% larger right
there.
You can stay with like metal zero and metal one.
Don't go to metal two like like here.
So you you you have less metal layers, but what's your area and
when we benchmark I CPU kind of logic block.
For four different technologies, four track Gate-all-around 6
trade gate-all-around, and then the sea fads for track five
track.
Uh, by the way, here we see.
Yeah, go ahead.
No, go ahead.
What's that?
Yeah.
So so one thing we see, by the way that might be, you know,
interesting for you if you if if the the the metal zero can
shrink down to 20 or like 19 then the library height is going
to be what 70 something 76 then you know these guys should be
like 10 and a meter and end to P should be high 20s.
So I don't know if you if you would need forksheet for that or
not, but you will have to get like 2:30 or or a little bit
less and to pee that's that's I think one of the observations.
You know the library will be limited by routing because
remember, TSMC tried uh short library with three signal tracks
and pretty much failed.
That didn't work.
You need 4 tracks and four tracks.
Will will get down to 80 or little bit less eventually.
So into P will be will be like 30 or to 25 in that range
anyway.
So so here what we see this is normalized metric.
The reference is 6 track gate-all-around and when we go
to other cases you can see that having 4 tracks is like more
important than staking transistors,.
So for tracks are much better for area and for power, and this
is like one over area times power.
But we see fire doesn't give you that much gain a versus
gate-all-around for logic.
For SRAM, it's a 2X area shrink, so it's it's a big deal for for
SRAM, but not for logic.
Because because SRAM bit cell is is basically inverter that you
can implement in 2 tracks.
Yeah.
So as I am can be two track logic yeah.
Yeah.
And then we also look at these, we play with the.
Pitches metal.
Two, pitch 3, three options here.
Metal one pitch either CPP 1 to one or half CPP, not three to
two.
Here we try.
You know half half CPP and we also played copper versus Molly.
Area here and power consumption.
There it's.
I isa either frequency, right?
So you can see.
So if you look at copper, if you shrink your metal one pitch in
half, great, great benefit like 20% area you know 20% power
consumption.
Uh, if you look at different metal, two pitch, not much
difference, but bigger pitch actually better.
So maybe 4 metal one.
The main differentiator here is is pin access.
If you have tighter metal, one pitch you have better PIN
excess.
You can route your stuff, connect metal two bigger Peach
gives you better resistance and and better you know performance
molybdenum is little bit better than copper and that was for low
power like 1 gigahertz.
If you go to three gigahertz high performance, qualitatively
similar picture, but Molly now becomes much better.
For this lower metal layers.
So you know, you probably have different answers for different
technologies, you know hyperformance versus mobile.
I mean to some extent it's almost like confusing so many
options to play this like, but you have to.
So maybe you need to to play with you know the logic blogs
that you have in mind and see what design rules work better
for that when you optimize it.
No, actually I was wondering.
One thing will eventually move down to CFET because the
topology, because the cell arrangement you will end up has
different if well thought process for the back end.
So when is tailored for one the other tailored for the other
right?
Yep, well, that'd be a possibility.
Send platform to see fat.
But you know what?
You have different interconnects scheme, which is a fundamentally
to process right?
I just cost then comes in, right?
What's the cost of?
Yeah.
Then you optimize the cost for functionality.
Yeah, yeah.
Yeah, actually, now we we we just implemented this cost
calculation capability with taking sides in into our tools.
So so you can plug in your process flow and see what's the
cost for different fab size and locations, you know, Arizona,
Taiwan.
This is full of felt today.
Right.
All process today.
Yeah.
For the positive future.
Uh.
Yeah, they have some.
Yeah, they have some estimates for future.
Really.
Yeah, yeah.
Ohh, I see.
That's Scott and Jones, kid.
He joined taken sides.
Ohh, he's doing cost OK.
Alright, industry logic road map.
So basically it used to be driven by pitch scaling, right?
But recently, Victor, perhaps just a quick process.
Check we have like a few minutes before end of that.
Yeah.
Or.
Yeah.
So what do you wanna do?
You can stop or we can go.
How many more on only like 4?
But yeah, out of the whole like, yeah, basically that's.
Yeah.
I I I think we can go to about 5 after a bunch of us have to
drop, but let's go.
Yeah, I think I have like 55 total, right.
Let's just aim for five after, if that's OK.
So 101012 more.
OK, but what?
So for the folks online, we will continue just go through the
5:00 o'clock and then depends our guests are the availability,
OK, what we just continue.
Yeah.
All right.
And you guys are welcome to drop off if you don't.
You cannot attend.
Yeah, so here reported anyway.
Yeah, here we see.
It's like, you know, making progress, maybe because people,
you know, come up with more skinning boosters over time, but
then we see density limit for 2D logic and then the only way to,
you know, go further would be cheap lights and stuff like
that.
And cryogenic yes.
So one issue is you know power consumption by data centers and
I just list here different issues.
The high VDD that's difficult to scale.
Interconnect capacitance and interconnect resistance, right.
So uh here.
There are several ideas thundering fed a negative
capacitance fed and and cold simos interconnect capacitance
scales as you scale the whole thing but PIN capacitance,
stopped because transistor is not moving much right and for
interconnects.
You know scaling, get makes it worse but but cooling makes it
better.
So thundering fat is failed and and you probably know this
already.
It's too too much variation and and not strong enough negative
capacitance, fair electric, you know fats, they are still being
tried for memory but not for logic anymore.
And for the cryogenic, as you call it, down, your Boltzmann
curse improves.
So there's a, you know, possibility to reduce VDD.
So what we see as we call it down from room temperature, the
VDD goes down and the self heating goes down as as as
temperature square quite a bit.
So if at room temperature you overhit by 60 degrees, then at
at at 4 Kelvin you were hit by 4 degrees at the same frequency
hardware.
So here the game becomes OK, you know that the power goes down as
as you cool it down, right?
But the question is how much and how much energy you spend to
cool it down.
So what what we did here, we look at CPU either frequency as
you call it down, it gets less, less, less, less like 14X less
power.
But then to cool down given power source like 100 Watt it it
takes more and more energy right as we go to lower temperatures.
But because we don't need fixed power, you know source it gets
lower and lower.
Basically what we need to cool it down is not monotonic.
You increase energy initially, but then it's less just because
you don't need that much to cool down.
If you add this up then it would be total ohh power by CPU and by
the the cooler.
So you see that it's monotonically going down, so any
cooling is beneficial.
You know a little bit cooling is beneficial.
The more cooling the better, and then we found that this is what
happens if you use standard technology.
But because gate, wait, wait.
I I went number I don't understand.
You go all the way to absolutely 044 Kelvin for Kelvin, but
electrical freeze out.
Not a four kill, and they still fine on the what's the material?
Silicon.
No.
Same stuff, no silicon will freeze out at the 40.
No, there there ionization probably only happen 80% or
less.
Yeah. Yeah, yeah.
Yeah.
So you're right, if there's no voltage, then it freezes out.
Yeah.
Once you apply more than like 20 millivolt on drain italianize
and we've seen we've seen Ivy Curves, if it's low low drain
bias less than like 15 minutes.
Self heating has to be very effective instead of counter the
argument couple of degrees is OK OK we've seen data from my
email.
They took TSMC technology measured down to 4 Kelvin.
You know, if it's low drain bias, it's like oscillating, but
you apply drain bias little bit and you're fine italianize it.
OK.
Uh, right.
So here just just illustration that that the gate leakage is a
strong function of the gate dielectric thickness but also
voltage.
So because we are not working at .8 we working at .2, we can
shrink the dielectric thickness you know from 1 nanometer to
half and then what we see is that you have additional 2X gain
in power, so.
I'm done.
Wait a minute.
No.
So cryogenic computing. Yeah.
Yeah.
So the thing we haven't looked at cost energy is good cost.
I don't know.
I mean, in the end at scale, can you let a I didn't look at cost?
No, actually I I think that the your charge if you can go back
to that chart, I thought that you know tried to get some
realistic assessment on that light blue or whatever the cyan
curve and that is a very useful, very looking to you know how to
balance the whole thing and especially you said hey because
you called down the phone and conduction getting better in
this also worth self heating is reduced great you know if so
then what that really mean in terms of the cooling down that
the somewhere energy and the inefficiency right.
So I think that curve is really needed.
OK.
India and it's like a how should we say it?
But basically, you're you're you're using your energy too.
I mean, cool down to to keep your scattering down right?
Umm to gain the power efficiency, but you're supplying
that power to cool the system. So it's.
Yeah, it's a bit interesting.
There is some some like a cost analysis or right not not dollar
but even the paper you have it in a way.
Umm.
Power.
Yes. Powers here.
Yeah.
And I consulted with Oxford Instruments to get this, you
know, cooling power curve.
Actually your last bullet is very interesting.
How?
How how people look into this or any of the referencing that is
77 Kelvin comparison to room temperature and the temperature.
What's the optimal temperature?
77 is great.
You know, we just some liquid nitrogen, right?
The the finition uh SOW for DARPA LTLT low temperature logic
technology with Intel.
I think Intel is primary and via secondary because Intel didn't
want to do silicon, you know wafers.
So it's modeling and we are doing it.
So the DARPA goal was 25X reduction and we didn't get, but
it was like dream, right?
So we found that this standard technology you can get down to
like 14X and with this thinner gate dielectric you can down
closer to 20X.
Not quite 25, but pretty close.
Interesting.
It's a long, long time ago I was working on the ETA 10.
Mm-hmm.
That was a 77K and it was judged not partical, and in that the
whole project and the scribed.
Mm-hmm.
Now it's a revisit also from that part.
OK.
No, but this is like a true bye.
Like you coming true, I mean, no, I just say realize what?
What has been changed?
That's why it says looking all those things is like a better,
you know, people start realizing there's more factory get get in.
Right, because back then, it was the the record.
It was the record is that no way.
We don't want to do that, so the whole project of expect now is
restarted and the what are the changing in fact this is not
changing but what we learn more such as we say that's the area
worst of the exploring, right?
Well, maybe you mean like it when?
When when power supply was five waltz and then you know, people
didn't really care right at that time, was 2.52 point five.
Well still your your below 3 vote.
That is the magic right threshold.
Slope was not the limiting factor.
OK, maybe that's why.
OK, but now it is alright.
Good, good.
The the the question for I don't know.
I'm leaving.
OK.
Yeah, question for Victor.
OK, great, Victor.
Thank you very much.
You're and your time.
Alright folks, the the OHS, the, the Victor of the size will be
available to Intel folks.
OK.
I'll I'll post the size on the SharePoint and the video also
too great.
Thank you.
Thank you very much, Victor.
Thank you. Great.
Uh, so we conclude for today's session.
Thank you.
Thank you for attending.
Bye bye.